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MSI Protocol
- Forms the foundation of invalidation-based writeback protocols
- Assumes only three supported cache line states: I, S, and M
- There may be multiple processors caching a line in S state
- There must be exactly one processor caching a line in M state and it is the owner of the line
- If none of the caches have the line, memory must have the most up-to-date copy of the line
State Transition
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