Module 9: Addendum to Module 6: Shared Memory Multiprocessors
  Lecture 18: Sharing Patterns and Cache Coherence Protocols
 


MOESI Protocol

  • State transitions pertaining to O state
    • I to O: Not possible
    • E to O or S to O: Not possible
    • M to O: On a BusRd /Flush (but no memory writeback )
    • O to I: On CacheEvict / BusWB or { BusRdX,BusUpgr }/Flush ]
    • O to S: Not possible
    • O to E: Not possible
    • O to M: On PrWr / BusUpgr
  • At most one cache can have a line in O state at any point in time
  • Two main design choices for MOESI
    • Consider the example: P0 reads x, P0 writes x, P1 reads x, P2 reads x, P3 reads x, …
    • When P1 launches BusRd , P0 sources the line and now the protocol has two options: 1. The line in P0 goes to O and the line in P1 is filled in state S; 2. The line in P0 goes to S and the line in P1 is filled in state O i.e. P1 inherits ownership from P0
    • For distributed shared memory, the second choice is better
    • According to the second choice, when P2 generates a BusRd request, P1 sources the line and transitions from O to S; P2 becomes the new owner