IBM POWER5

• Dynamic power management
  • With SMT and CMP average number of switching per cycle increases leading to more power consumption
  • Need to reduce power consumption without losing performance: simple solution is to clock it at a slower frequency, but that hurts performance
  • POWER5 employs fine-grain clock-gating: in every cycle the power management logic decides if a certain latch will be used in the next cycle; if not, it disables or gates the clock for that latch so that it will not unnecessarily switch in the next cycle
  • Clock-gating and power management logic themselves should be very simple
  • If both threads are running at priority level 1, the processor switches to a low power mode where it dispatches instructions at a much slower pace

POWER5 Die Photo