Module 8: Memory Consistency Models and Case Studies of Multi-core
  Lecture 16: Case Studies of Multi-core
 


Intel Montecito

Features

  • Dual core Itanium 2, each core dual threaded
  • 1.7 billion transistors, 21.5 mm x 27.7 mm die
  • 27 MB of on-chip three levels of cache
    • Not shared among cores
  • 1.8+ GHz, 100 W
  • Single-thread enhancements
    • Extra shifter improves performance of crypto codes by 100%
    • Improved branch prediction
    • Improved data and control speculation recovery
    • Separate L2 instruction and data caches buys 7% improvement over Itanium2; four times bigger L2I (1 MB)
    • Asynchronous 12 MB L3 cache

Overview