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IBM POWER5
- Same pipeline structure as POWER4
- Added SMT facility
- Like Pentium 4, fetches from each thread in alternate cycles (8-instruction fetch per cycle just like POWER4)
- Threads share ITLB and ICache
- Increased size of register file compared to POWER4 to support two threads: 120 integer and floating-point registers (POWER4 has 80 integer and 72 floating-point registers): improves single-thread performance compared to POWER4; smaller technology (0.13 µ m) made it possible to access a bigger register file in same or shorter time leading to same pipeline as POWER4
- Doubled associativity of L1 caches to reduce conflict misses: icache is 2-way and dcache is 4-way
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