Hardware Support

• Start with a simple software lock

  Shared: lock = 0;
  Acquire : while (lock); lock = 1;
  Release or Unlock : lock = 0;

• Assembly translation

Lock: lw register, lock_addr /* register is any processor register */
bnez register, Lock
addi register, register, 0x1
sw register, lock_addr
Unlock: xor register, register, register
sw register, lock_addr

• Does it work?

• What went wrong?
• We wanted the read-modify-write sequence to be atomic

Atomic Exchange

• We can fix this if we have an atomic exchange instruction

  addi register, r0, 0x1	/* r0 is hardwired to 0 */
  Lock: xchg register, lock_addr	/* An atomic load and store */

  bnez register, Lock
  Unlock remains unchanged

• Various processors support this type of instruction
  • Intel x86 has xchg , Sun UltraSPARC has ldstub (load-store-unsigned byte), UltraSPARC also has swap
  • Normally easy to implement for bus-based systems: whoever wins the bus for xchg can lock the bus
  • Difficult to support in distributed memory systems