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MESI Protocol
- The most popular invalidation-based protocol e.g., appears in Intel Xeon MP
- Why need E state?
- The MSI protocol requires two transactions to go from I to M even if there is no intervening requests for the line: BusRd followed by BusUpgr
- We can save one transaction by having memory controller respond to the first BusRd with E state if there is no other sharer in the system
- How to know if there is no other sharer? Needs a dedicated control wire that gets asserted by a sharer (wired OR)
- Processor can write to a line in E state silently and take it to M state
State Transition
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