MESI Protocol

• If a cache line is in M state definitely the processor with the line is responsible for flushing it on the next BusRd or BusRdX transaction
• If a line is not in M state who is responsible?
  • Memory or other caches in S or E state?
  • Original Illinois MESI protocol assumed cache-to-cache transfer i.e. any processor in E or S state is responsible for flushing the line
• However, it requires some expensive hardware, namely, if multiple processors are caching the line in S state who flushes it? Also, memory needs to wait to know if it should source the line
• Without cache-to-cache sharing memory always sources the line unless it is in M state

MESI Example

• Take the following example
  • P0 reads x, P0 writes x, P1 reads x, P1 writes x, …

P0 generates BusRd , memory provides line, P0 puts line in cache in E state
P0 does write silently, goes to M state
P1 generates BusRd , P0 provides line, P1 puts line in cache in S state, P0 transitions to S state
Rest is identical to MSI

• Consider this example: P0 reads x, P1 reads x, …

P0 generates BusRd , memory provides line, P0 puts line in cache in E state
P1 generates BusRd , memory provides line, P1 puts line in cache in S state, P0 transitions to S state (no cache-to-cache sharing)
Rest is same as MSI