M to S, or M to I?

• BusRd takes a cache line in M state to S state
  • The assumption here is that the processor will read it soon, so save a cache miss by going to S
  • May not be good if the sharing pattern is migratory : P0 reads and writes cache line A, then P1 reads and writes cache line A, then P2…
• For migratory patterns it makes sense to go to I state so that a future invalidation is saved
• But for bus-based SMPs it does not matter much because an upgrade transaction will be launched anyway by the next writer, unless there is special hardware support to avoid that: how?
• The big problem is that the sharing pattern for a cache line may change dynamically: adaptive protocols are good and are supported by Sequent Symmetry and MIT Alewife

MSI Example

• Take the following example
  • P0 reads x, P1 reads x, P1 writes x, P0 reads x, P2 reads x, P3 writes x
  • Assume the state of the cache line containing the address of x is I in all processors

  P0 generates BusRd , memory provides line, P0 puts line in S state
  P1 generates BusRd , memory provides line, P1 puts line in S state
  P1 generates BusUpgr , P0 snoops and invalidates line, memory does not respond, P1 sets state of line to M
  P0 generates BusRd , P1 flushes line and goes to S state, P0 puts line in S state, memory writes back
  P2 generates BusRd , memory provides line, P2 puts line in S state
  P3 generates BusRdX , P0, P1, P2 snoop and invalidate, memory provides line, P3 puts line in cache in M state