State Transition

• The finite state machine for each cache line:

• On a write miss no line is allocated
  • The state remains at I: called write through write no-allocated
• A/B means: A is generated by processor, B is the resulting bus transaction (if any)
• Changes for write through write allocate?

Ordering Memory op

• Assume that the bus is atomic
  • It takes up the next transaction only after finishing the previous one
• Read misses and writes appear on the bus and hence are visible to all processors
• What about read hits?
  • They take place transparently in the cache
  • But they are correct as long as they are correctly ordered with respect to writes
• And all writes appear on the bus and hence are visible immediately in the presence of an atomic bus
• In general, in between writes reads can happen in any order without violating coherence
  • Writes establish a partial order