Module 6: Shared Memory Multiprocessors: Consistency and Coherence
  Lecture 11: Introduction to Snoopy Coherence
 


Snoopy Protocols

  • Cache coherence protocols implemented in bus-based machines are called snoopy protocols
    • The processors snoop or monitor the bus and take appropriate protocol actions based on snoop results
    • Cache controller now receives requests both from processor and bus
    • Since cache state is maintained on a per line basis that also dictates the coherence granularity
    • Cannot normally take a coherence action on parts of a cache line
    • The coherence protocol is implemented as a finite state machine on a per cache line basis
    • The snoop logic in each processor grabs the address from the bus and decides if any action should be taken on the cache line containing that address (only if the line is in cache)

Write Through Caches

  • There are only two cache line states
    • Invalid (I): not in cache
    • Valid (V): present in cache, may be present in other caches also
  • Read access to a cache line in I state generates a BusRd request on the bus
    • Memory controller responds to the request and after reading from memory launches the line on the bus
    • Requester matches the address and picks up the line from the bus and fills the cache in V state
    • A store to a line always generates a BusWr transaction on the bus (since write through); other sharers either invalidate the line in their caches or update the line with new value