Write Through is Bad

• High bandwidth requirement
  • Every write appears on the bus
  • Assume a 3 GHz processor running application with 10% store instructions, assume CPI of 1
  • If the application runs for 100 cycles it generates 10 stores; assume each store is 4 bytes; 40 bytes are generated per 100/3 ns i.e. BW of 1.2 GB/s
• A 1 GB/s bus cannot even support one processor
• There are multiple processors and also there are read misses
• Writeback caches absorb most of the write traffic
  • Writes that hit in cache do not go on bus (not visible to others)
  • Complicated coherence protocol with many choices

Memory Consistency

• Need a more formal description of memory ordering
  • How to establish the order between reads and writes from different processors?
• The most clear way is to use synchronization

  P0: A=1; flag=1
  P1: while (!flag); print A;

• Another example (assume A=0, B=0 initially)

  P0: A=1; print B;
  P1: B=1; print A;

  • What do you expect?
• Memory consistency model is a contract between programmer and hardware regarding memory ordering