Unpipelined Microprocessors

• Typically an instruction enjoys five phases in its life
  • Instruction fetch from memory
  • Instruction decode and operand register read
  • Execute
  • Data memory access
  • Register write
• Unpipelined execution would take a long single cycle or multiple short cycles
  • Only one instruction inside processor at any point in time

Pipelining

• One simple observation
  • Exactly one piece of hardware is active at any point in time
• Why not fetch a new instruction every cycle?
  • Five instructions in five different phases
  • Throughput increases five times (ideally)
• Bottom-line is
  • If consecutive instructions are independent, they can be processed in parallel
  • The first form of instruction-level parallelism (ILP)