Module 1: Multi-core: The Ultimate Dose of Moore's Law
  Lecture 1: Evolution of Processor Architecture
 


Pipelining Hazards

  • Instruction dependence limits achievable parallelism
    • Control and data dependence (aka hazards)
  • Finite amount of hardware limits achievable parallelism
    • Structural hazards
  • Control dependence
    • On average, every fifth instruction is a branch (coming from if-else, for, do-while,…)
    • Branches execute in the third phase
      • Introduces bubbles unless you are smart

Control Dependence

What do you fetch in X and Y slots?

Options: Nothing, fall-through, learn past history and predict (today best predictors achieve on average 97% accuracy for SPEC2000)

Data Dependence