Addressing a cache

• The PA is divided into several parts
• The block offset determines the starting byte address within a cache line
• The index tells you which cache line to access
• In that cache line you compare the tag to determine hit/miss
• An example
  • PA is 32 bits
  • Cache line is 64 bytes: block offset is 6 bits
  • Number of cache lines is 512: index is 9 bits
  • So tag is the remaining bits: 17 bits
  • Total size of the cache is 512*64 bytes i.e. 32 KB
  • Each cache line contains the 64 byte data, 17-bit tag, one valid/invalid bit, and several state bits (such as shared, dirty etc.)
  • Since both the tag and the index are derived from the PA this is called a physically indexed physically tagged cache