TLB

• Why can’t we cache the most recently used translations?
  • Translation Look-aside Buffers (TLB)
  • Small set of registers (normally fully associative)
  • Each entry has two parts: the tag which is simply VPN and the corresponding PTE
  • The tag may also contain a process id
  • On a TLB hit you just get the translation in one cycle (may take slightly longer depending on the design)
  • On a TLB miss you may need to access memory to load the PTE in TLB (more later)
  • Normally there are two TLBs: instruction and data

Caches

• Once you have completed the VA to PA translation you have the physical address. What’s next?
• You need to access memory with that PA
• Instruction and data caches hold most recently used (temporally close) and nearby (spatially close) data
• Use the PA to access the cache first
• Caches are organized as arrays of cache lines
• Each cache line holds several contiguous bytes (32, 64 or 128 bytes)