Module 4: "Recap: Virtual Memory and Caches"
  Lecture 7: "Virtual Memory, TLB, and Caches"
 

VA to PA translation

  • The VA generated by the processor is divided into two parts:
    • Page offset and Virtual page number (VPN)
    • Assume a 4 KB page: within a 32-bit VA, lower 12 bits will be page offset (offset within a page) and the remaining 20 bits are VPN (hence 1 M virtual pages total)
    • The page offset remains unchanged in the translation
    • Need to translate VPN to a physical page frame number (PPFN)
    • This translation is held in a page table resident in memory: so first we need to access this page table
    • How to get the address of the page table?
  • Accessing the page table
    • The Page table base register (PTBR) contains the starting physical address of the page table
    • PTBR is normally accessible in the kernel mode only
    • Assume each entry in page table is 32 bits (4 bytes)
    • Thus the required page table address is
    • Access memory at this address to get 32 bits of data from the page table entry (PTE)
    • These 32 bits contain many things: a valid bit, the much needed PPFN (may be 20 bits for a 4 GB physical memory), access permissions (read, write, execute), a dirty/modified bit etc.

Page fault

  • The valid bit within the 32 bits tells you if the translation is valid
  • If this bit is reset that means the page is not resident in memory: results in a page fault
  • In case of a page fault the kernel needs to bring in the page to memory from disk
  • The disk address is normally provided by the page table entry (different interpretation of 31 bits)
  • Also kernel needs to allocate a new physical page frame for this virtual page
  • If all frames are occupied it invokes a page replacement policy

VA to PA translation

  • Page faults take a long time: order of ms
    • Need a good page replacement policy
  • Once the page fault finishes, the page table entry is updated with the new VPN to PPFN mapping
  • Of course, if the valid bit was set, you get the PPFN right away without taking a page fault
  • Finally, PPFN is concatenated with the page offset to get the final PA 
  • Processor now can issue a memory request with this PA to get the necessary data
  • Really two memory accesses are needed
  • Can we improve on this?