When another processor wishes to read this block, the data are sent to this processor by the current owner.
The data are also sent to the home memory module, which requires ownership and updates the block to contain the latest value.
There are software and hardware solutions for cache coherence problem.
In software approach, the detecting of potential cache coherence problem is transferred from run time to compile time, and the design complexity is transferred from hardware to software
On the other hand, compile time software approaches generally make conservative decisions, leading to inefficient cache utilization.
Compiler-based cache coherence mechanism perform an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly. So, there are some non cacheable items, and the operating system or hardware does not cache those items.
The simplest approach is to prevent any shared data variables from being cached.