In contemporary multiprocessor system, it is customary to have one or two levels of cache associated with each processor. This organization is essential to achieve high performance.
Cache creates a problem, which is known as the cache coherence problem. The cache coherence problem is : Multiple copies of the same data can exist in different caches simultaneously, and if processors are allowed to update their own copies freely, an inconsistent view of memory can result.
There are two write policies:
- Write back : Write operations are usually made only to the cache. Main memory is only updated when the corresponding cache line is flushed from the cache.
- Write through : All write operations are made to main memory as well as to the cache, ensuring that main memory is always valid.
It is clear that a write back policy can result in inconsistency.
If two caches contain the same line, and the line is updated in one cache, the other cache will unknowingly have an invalid value. Subsequently read to that invalid line produce invalid results.