In clock cycle 1,  the master sends address and command on the bus requesting a read operation.

The target device responded at clock cycle 3 by indicating that it is ready to participate in the data transfer by making the slave ready signal high.

Then the target device places the data on the data line.

The target device is a slower device and it needs two clock cycle to transfer the information. After two clock cycle, that is at clock cycle 5, it pulls down the slave ready signal down.

When the slave ready signal goes down, the master strobes the data from the data bus into its input buffer.

If the addressed device does not respond at all, the master waits for some predefined maximum number of clock cycles, then aborts the operation.