In asynchronous mode of transfer, a handshake signal is used between master and slave.
In asynchronous bus, there is no common clock, and the common clock signal is replaced by two timing control signals: master-ready and slave-ready.
Master-ready signal is assured by the master to indicate that it is ready for a transaction, and slave-ready signal is a response from the slave.
The handshaking protocol proceeds as follows:
- The master places the address and command information on the bus. Then it indicates to all devices that it has done so by activating the master-ready signal.
- This causes all devices on the bus to decode the address.
- The selected target device performs the required operation and inform the processor (or master) by activating the slave-ready line.
- The master waits for slave-ready to become asserted before it remove its signals from the bus.
- In case of a read operation, it also strobes the data into its input buffer.