The simple design of device interface by synchronous bus has some limitations.
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A transfer has to be completed within one clock cycle. The clock period, must be long enough to accommodate the slowest device to interface. This forces all devices to operate at the speed of slowest device.
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The processor or the master has no way to determine whether the addressed device has actually responded. It simply assumes that, the output data have been received by the device or the input data are available on the data lines.
To solve these problems, most buses incorporate control signals that represent a response from the device. These signals inform the master that the target device has recognized its address and it is ready to participate in the data transfer operation.
They also adjust the duration of the data transfer period to suit the needs of the participating devices.
A high frequency clock pulse is used so that a complete data transfer operation span over several clock cycles. The numbers of clock cycles involved can vary from device to device