At the end of the clock cycle, at time t2, the master strobes the data on the data lines into its input buffer. The period t2- t1 must be greater than the maximum propagation delay on the bus plus the set up time of the input buffer register of the master.
A similar procedure is followed for an output operation. The master places the output data on the data lines when it transmits the address and command information. At time t2, the addressed device strobe the data lines and load the data into its data buffer.