Let us consider the sequence of events during an input (read) operation.

At time t₀, the master places the device address on the address lines and sends an appropriate command (read in case of input) on the command lines.

In any data transfer operation, one device plays the role of a master, which initiates data transfer by issuing read or write commands on the bus.

Normally, the processor acts as the master, but other device with DMA capability may also becomes bus master. The device addressed by the master is referred to as a slave or target device.

The command also indicates the length of the operand to be read, if necessary.

The clock pulse width, t₁ - t₀, must be longer than the maximum propagation delay between two devices connected to the bus.

After decoding the information on address and control lines by slave, the slave device of that particular address responds at time t₁. The addressed slave device places the required input data on the data line at time .