Course abstract
The course will introduce students to the topics of Digital CMOS VLSI subsystem design using design metrics of delay, power, and area in detail. The course focuses more on power estimation, and interconnect aware designs and discusses on few power benefits designs. Approximate computing datapath subsystem designs will be analyzed along with the design, and error metrics. Different forms of standard cell design of latch, and flipflops will be discussed and the importance of timing parameters in sequential circuits will explained.
Course Instructor
Prof. Madhav Rao
Prof.Madhav Rao is an Associate Professor at IIIT-Bangalore. He teaches Digital VLSI Design, VLSI subsystem, Electronic devices and circuits, and basic electronics courses to IIIT-B students. He is a recipient of SERB Early Career Research Award (2014-2017), Visvesvaraya Young Faculty fellowship award (2016-2020), IBM Shared University Research Award (2018-20), 2021 IBM Global University Program Academic Award. He has also completed projects sponsored by MEITY in the past, and is currently involved in the project from MSJE, and GoK, IT-BT center.More info
Teaching Assistant(s)
No teaching assistant data available for this course yetCourse Duration : Jan-Apr 2022
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Enrollment : 14-Nov-2021 to 31-Jan-2022
Exam registration : 13-Dec-2021 to 18-Mar-2022
Exam Date : 24-Apr-2022
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Certified Category Count
Gold
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Silver
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Elite
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Category : Successfully Completed
Elite
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Category : Elite
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Category : Gold