| Name | Download | Download Size |
|---|---|---|
| Lecture Note | Download as zip file | 7.4M |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Course Contents, Objective | Download Verified |
| 2 | Revision of Prerequisite | Download Verified |
| 3 | Design of Synchronous Sequential Circuits | Download Verified |
| 4 | Analysis of Synchronous Sequential Circuits | Download Verified |
| 5 | Top-down Design | Download Verified |
| 6 | Controller Design | Download Verified |
| 7 | Control algorithm and State diagram | Download Verified |
| 8 | Case study 1 | Download Verified |
| 9 | Entity, Architecture and Operators | Download Verified |
| 10 | Concurrency, Data flow and Behavioural models | Download Verified |
| 11 | Structural Model, Simulation | Download Verified |
| 12 | Simulating Concurrency | Download Verified |
| 13 | Classes and Data types | Download Verified |
| 14 | Concurrent statements and Sequential statements | Download Verified |
| 15 | Sequential statements and Loops | Download Verified |
| 16 | Modelling flip-flops, Registers | Download Verified |
| 17 | Synthesis of Sequential circuits | Download Verified |
| 18 | Libraries and Packages | Download Verified |
| 19 | Operators, Delay modelling | Download Verified |
| 20 | Delay modelling | Download Verified |
| 21 | VHDL Examples | Download Verified |
| 22 | VHDL Examples, FSM Clock | Download Verified |
| 23 | FSM issues 1 | Download Verified |
| 24 | FSM Issues 2 | Download Verified |
| 25 | FSM Issues 3 | Download Verified |
| 26 | VHDL coding of FSM | Download Verified |
| 27 | FSM Issues 4 | Download Verified |
| 28 | FSM Issues 5 | Download Verified |
| 29 | Synchronization 1 | Download Verified |
| 30 | Synchronization 2 | Download Verified |
| 31 | Evolution of PLDs | Download Verified |
| 32 | Simple PLDs | Download Verified |
| 33 | Simple PLDs: Fitting | Download Verified |
| 34 | Complex PLDs | Download Verified |
| 35 | FPGA Introduction | Download Verified |
| 36 | FPGA Interconnection, Design Methodology | Download Verified |
| 37 | Xilinx Virtex FPGA’s CLB | Download Verified |
| 38 | Xilinx Virtex Resource Mapping, IO Block | Download Verified |
| 39 | Xilinx Virtex Clock Tree | Download Verified |
| 40 | FPGA Configuration | Download Verified |
| 41 | Altera and Actel FPGAs | Download Verified |
| 42 | VHDL Test bench | Download Verified |
| 43 | Case study 2 | Download Verified |
| 44 | Case study on FPGA Board | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |