Sl.No | Chapter Name | MP4 Download |
---|---|---|
1 | 1.1 - Understanding Silicon | Download |
2 | 1.2 - Introduction to NMOS | Download |
3 | 1.3 - NMOS Transistor Working | Download |
4 | 1.4 - PMOS Transistor | Download |
5 | 1.5 - MOS Capacitances | Download |
6 | 1.6 - Non Ideal MOS model | Download |
7 | 1.7 - Short channel current model | Download |
8 | 1.8 - Short channel current model analysis | Download |
9 | 2.1 - Channel Length modulation index | Download |
10 | 2.2 - DC characteristics of Inverter | Download |
11 | 2.3 - Transfer characteristics of Inverter | Download |
12 | 2.4 - Skewed Inverter | Download |
13 | 2.5 - Skewed Inverter and threshold voltage | Download |
14 | 2.6 - Equivalent of transistors in series | Download |
15 | 2.7 - Transmission Gate | Download |
16 | 3.1 - Bad CMOS Buffer - Part1 | Download |
17 | 3.2 - Bad CMOS Buffer - Part2 | Download |
18 | 3.3 - Noise margin characteristics of inverter | Download |
19 | 3.4 - Noise margin parameters | Download |
20 | 3.5 - Introduction to Delay in CMOS | Download |
21 | 3.6 - Transient analysis of CMOS Inverter | Download |
22 | 3.7 - RC approximated delay | Download |
23 | 3.8 - Switching Resistance | Download |
24 | 4.1 - CMOS Inverter approximated to RC Circuit | Download |
25 | 4.2 - Elmore delay | Download |
26 | 4.3 - Delay of FO4 inverter | Download |
27 | 4.4 - Extracting capacitances of 3-Nand gate for delay estimation | Download |
28 | 4.5 - Characterizing Delay of NOR gate | Download |
29 | 4.6 - Linear Delay model | Download |
30 | 4.7 - Logical effort and Parasitic delay | Download |
31 | 5.1 - Logical effort and Parasitic delay for different gates | Download |
32 | 5.2 - Logical effort for short-channel current model | Download |
33 | 5.3 - Ring Oscillator design | Download |
34 | 5.4 - Optimizing Gate Size | Download |
35 | 5.5 - Optimizing Gate Sizes Example | Download |
36 | 5.6 - Optimizing the Stages for an inverter path | Download |
37 | 5.7 - Optimizing the Stages for a General Circuit | Download |
38 | 5.8 - Decoder Design | Download |
39 | 6.1 - Introduction to Combinational Circuit and assymetric gates | Download |
40 | 6.2 - Assymetric Gates analysis | Download |
41 | 6.3 - Assymetric Gates analysis using short-channel current model | Download |
42 | 6.4 - Introduction to Skewed gates | Download |
43 | 6.5 - Skewed gates and best P/N ratio | Download |
44 | 6.6 - vIntroduction to Pseudo NMOS | Download |
45 | 6.7 - Psudeo NMOS gates | Download |
46 | 6.8 - Other Logic Family | Download |
47 | 6.9 - Dynamic Logic and Domino logic | Download |
48 | 7.1 - Domino gates | Download |
49 | 7.2 - Introduction to Stick Diagram | Download |
50 | 7.3 - Stick Diagram for different gates | Download |
51 | 7.4 - Applying Eulers path for stick diagram representations | Download |
52 | 7.5 - Multiplexer design and layout | Download |
53 | 7.6 - Introduction to Interconnects | Download |
54 | 7.7 - Interconnects - RC delay, and Energy | Download |
55 | 8.1 - Introduction to crosstalks in interconnects | Download |
56 | 8.2 - Transient analysis in Crosstalk | Download |
57 | 8.3 - Introduction to Repeaters in Interconnect Engineering | Download |
58 | 8.4 - Repeater Design | Download |
59 | 8.5 - Energy and delay analysis for interconnectwith repeaters | Download |
60 | 8.6 - Repeater Design and Energy-Delay-Product | Download |
61 | 8.7 - Introduction to Power | Download |
62 | 9.1 - Switching Power and Energy Estimation | Download |
63 | 9.2 - Activity factor and estimating dynamic power for a combinational circuit design | Download |
64 | 9.3 - Analyzing Dynamic Power | Download |
65 | 9.4 - Energy estimation through driving factor | Download |
66 | 9.5 - Energy expression in terms of delay | Download |
67 | 9.6 - Voltage Scaling | Download |
68 | 9.7 - DVFS | Download |
69 | 10.1 - Introduction to subthreshold leakage current model | Download |
70 | 10.2 - Subthreshold leakage current and Gate leakage current | Download |
71 | 10.3 - Estimating Static Power | Download |
72 | 10.4 - Introduction to CMOS Latch design | Download |
73 | 10.5 - CMOS Latch Design | Download |
74 | 10.6 - CMOS Latch and flipflop design | Download |
75 | 11.1 - Static Timing Analysis | Download |
76 | 11.2 - Static Timing Analysis - Continued | Download |
77 | 11.3 - Static Timing Analysis - Part2 | Download |
78 | 11.4 - Static Timing Analysis - Part2.1 | Download |
79 | 11.5 - Static Timing Analysis - Part3 | Download |
80 | 11.6 - TPDQ and TPCQ | Download |
81 | 11.7 - Static Timing Analysis - Part4 | Download |
82 | 11.8 - Static Timing Analysis - Part5 | Download |
83 | 11.9 - Static Timing Analysis - Part6 | Download |
84 | 11.10 - SET and CLEAR enabled Latch and Flipflop Design | Download |
85 | 12.1 - 1-bit Adder design | Download |
86 | 12.2 - Adder-Part2 | Download |
87 | 12.3 - PG architecture - Part1 | Download |
88 | 12.4 - PG architecture - Part2 | Download |
89 | 12.5 - Carry Skip Adder | Download |
90 | 12.6 - Carry Look Ahead and Carry Increment Adder | Download |
91 | 12.7 - Other Adder Subsystems | Download |
92 | 12.8 - Approximate Multipliers - Part 1 | Download |
93 | 12.9 - Approximate Multipliers - Part 2 | Download |
94 | 12.10 - Approximate Adder | Download |
Sl.No | Chapter Name | English |
---|---|---|
1 | 1.1 - Understanding Silicon | PDF unavailable |
2 | 1.2 - Introduction to NMOS | PDF unavailable |
3 | 1.3 - NMOS Transistor Working | PDF unavailable |
4 | 1.4 - PMOS Transistor | PDF unavailable |
5 | 1.5 - MOS Capacitances | PDF unavailable |
6 | 1.6 - Non Ideal MOS model | PDF unavailable |
7 | 1.7 - Short channel current model | PDF unavailable |
8 | 1.8 - Short channel current model analysis | PDF unavailable |
9 | 2.1 - Channel Length modulation index | PDF unavailable |
10 | 2.2 - DC characteristics of Inverter | PDF unavailable |
11 | 2.3 - Transfer characteristics of Inverter | PDF unavailable |
12 | 2.4 - Skewed Inverter | PDF unavailable |
13 | 2.5 - Skewed Inverter and threshold voltage | PDF unavailable |
14 | 2.6 - Equivalent of transistors in series | PDF unavailable |
15 | 2.7 - Transmission Gate | PDF unavailable |
16 | 3.1 - Bad CMOS Buffer - Part1 | PDF unavailable |
17 | 3.2 - Bad CMOS Buffer - Part2 | PDF unavailable |
18 | 3.3 - Noise margin characteristics of inverter | PDF unavailable |
19 | 3.4 - Noise margin parameters | PDF unavailable |
20 | 3.5 - Introduction to Delay in CMOS | PDF unavailable |
21 | 3.6 - Transient analysis of CMOS Inverter | PDF unavailable |
22 | 3.7 - RC approximated delay | PDF unavailable |
23 | 3.8 - Switching Resistance | PDF unavailable |
24 | 4.1 - CMOS Inverter approximated to RC Circuit | PDF unavailable |
25 | 4.2 - Elmore delay | PDF unavailable |
26 | 4.3 - Delay of FO4 inverter | PDF unavailable |
27 | 4.4 - Extracting capacitances of 3-Nand gate for delay estimation | PDF unavailable |
28 | 4.5 - Characterizing Delay of NOR gate | PDF unavailable |
29 | 4.6 - Linear Delay model | PDF unavailable |
30 | 4.7 - Logical effort and Parasitic delay | PDF unavailable |
31 | 5.1 - Logical effort and Parasitic delay for different gates | PDF unavailable |
32 | 5.2 - Logical effort for short-channel current model | PDF unavailable |
33 | 5.3 - Ring Oscillator design | PDF unavailable |
34 | 5.4 - Optimizing Gate Size | PDF unavailable |
35 | 5.5 - Optimizing Gate Sizes Example | PDF unavailable |
36 | 5.6 - Optimizing the Stages for an inverter path | PDF unavailable |
37 | 5.7 - Optimizing the Stages for a General Circuit | PDF unavailable |
38 | 5.8 - Decoder Design | PDF unavailable |
39 | 6.1 - Introduction to Combinational Circuit and assymetric gates | PDF unavailable |
40 | 6.2 - Assymetric Gates analysis | PDF unavailable |
41 | 6.3 - Assymetric Gates analysis using short-channel current model | PDF unavailable |
42 | 6.4 - Introduction to Skewed gates | PDF unavailable |
43 | 6.5 - Skewed gates and best P/N ratio | PDF unavailable |
44 | 6.6 - vIntroduction to Pseudo NMOS | PDF unavailable |
45 | 6.7 - Psudeo NMOS gates | PDF unavailable |
46 | 6.8 - Other Logic Family | PDF unavailable |
47 | 6.9 - Dynamic Logic and Domino logic | PDF unavailable |
48 | 7.1 - Domino gates | PDF unavailable |
49 | 7.2 - Introduction to Stick Diagram | PDF unavailable |
50 | 7.3 - Stick Diagram for different gates | PDF unavailable |
51 | 7.4 - Applying Eulers path for stick diagram representations | PDF unavailable |
52 | 7.5 - Multiplexer design and layout | PDF unavailable |
53 | 7.6 - Introduction to Interconnects | PDF unavailable |
54 | 7.7 - Interconnects - RC delay, and Energy | PDF unavailable |
55 | 8.1 - Introduction to crosstalks in interconnects | PDF unavailable |
56 | 8.2 - Transient analysis in Crosstalk | PDF unavailable |
57 | 8.3 - Introduction to Repeaters in Interconnect Engineering | PDF unavailable |
58 | 8.4 - Repeater Design | PDF unavailable |
59 | 8.5 - Energy and delay analysis for interconnectwith repeaters | PDF unavailable |
60 | 8.6 - Repeater Design and Energy-Delay-Product | PDF unavailable |
61 | 8.7 - Introduction to Power | PDF unavailable |
62 | 9.1 - Switching Power and Energy Estimation | PDF unavailable |
63 | 9.2 - Activity factor and estimating dynamic power for a combinational circuit design | PDF unavailable |
64 | 9.3 - Analyzing Dynamic Power | PDF unavailable |
65 | 9.4 - Energy estimation through driving factor | PDF unavailable |
66 | 9.5 - Energy expression in terms of delay | PDF unavailable |
67 | 9.6 - Voltage Scaling | PDF unavailable |
68 | 9.7 - DVFS | PDF unavailable |
69 | 10.1 - Introduction to subthreshold leakage current model | PDF unavailable |
70 | 10.2 - Subthreshold leakage current and Gate leakage current | PDF unavailable |
71 | 10.3 - Estimating Static Power | PDF unavailable |
72 | 10.4 - Introduction to CMOS Latch design | PDF unavailable |
73 | 10.5 - CMOS Latch Design | PDF unavailable |
74 | 10.6 - CMOS Latch and flipflop design | PDF unavailable |
75 | 11.1 - Static Timing Analysis | PDF unavailable |
76 | 11.2 - Static Timing Analysis - Continued | PDF unavailable |
77 | 11.3 - Static Timing Analysis - Part2 | PDF unavailable |
78 | 11.4 - Static Timing Analysis - Part2.1 | PDF unavailable |
79 | 11.5 - Static Timing Analysis - Part3 | PDF unavailable |
80 | 11.6 - TPDQ and TPCQ | PDF unavailable |
81 | 11.7 - Static Timing Analysis - Part4 | PDF unavailable |
82 | 11.8 - Static Timing Analysis - Part5 | PDF unavailable |
83 | 11.9 - Static Timing Analysis - Part6 | PDF unavailable |
84 | 11.10 - SET and CLEAR enabled Latch and Flipflop Design | PDF unavailable |
85 | 12.1 - 1-bit Adder design | PDF unavailable |
86 | 12.2 - Adder-Part2 | PDF unavailable |
87 | 12.3 - PG architecture - Part1 | PDF unavailable |
88 | 12.4 - PG architecture - Part2 | PDF unavailable |
89 | 12.5 - Carry Skip Adder | PDF unavailable |
90 | 12.6 - Carry Look Ahead and Carry Increment Adder | PDF unavailable |
91 | 12.7 - Other Adder Subsystems | PDF unavailable |
92 | 12.8 - Approximate Multipliers - Part 1 | PDF unavailable |
93 | 12.9 - Approximate Multipliers - Part 2 | PDF unavailable |
94 | 12.10 - Approximate Adder | PDF unavailable |
Sl.No | Language | Book link |
---|---|---|
1 | English | Not Available |
2 | Bengali | Not Available |
3 | Gujarati | Not Available |
4 | Hindi | Not Available |
5 | Kannada | Not Available |
6 | Malayalam | Not Available |
7 | Marathi | Not Available |
8 | Tamil | Not Available |
9 | Telugu | Not Available |