Modules / Lectures


Sl.No Chapter Name MP4 Download
11.1 - Understanding SiliconDownload
21.2 - Introduction to NMOSDownload
31.3 - NMOS Transistor WorkingDownload
41.4 - PMOS TransistorDownload
51.5 - MOS CapacitancesDownload
61.6 - Non Ideal MOS modelDownload
71.7 - Short channel current modelDownload
81.8 - Short channel current model analysisDownload
92.1 - Channel Length modulation indexDownload
102.2 - DC characteristics of InverterDownload
112.3 - Transfer characteristics of InverterDownload
122.4 - Skewed InverterDownload
132.5 - Skewed Inverter and threshold voltageDownload
142.6 - Equivalent of transistors in seriesDownload
152.7 - Transmission GateDownload
163.1 - Bad CMOS Buffer - Part1Download
173.2 - Bad CMOS Buffer - Part2Download
183.3 - Noise margin characteristics of inverterDownload
193.4 - Noise margin parametersDownload
203.5 - Introduction to Delay in CMOSDownload
213.6 - Transient analysis of CMOS InverterDownload
223.7 - RC approximated delayDownload
233.8 - Switching ResistanceDownload
244.1 - CMOS Inverter approximated to RC CircuitDownload
254.2 - Elmore delayDownload
264.3 - Delay of FO4 inverterDownload
274.4 - Extracting capacitances of 3-Nand gate for delay estimationDownload
284.5 - Characterizing Delay of NOR gateDownload
294.6 - Linear Delay modelDownload
304.7 - Logical effort and Parasitic delayDownload
315.1 - Logical effort and Parasitic delay for different gatesDownload
325.2 - Logical effort for short-channel current modelDownload
335.3 - Ring Oscillator designDownload
345.4 - Optimizing Gate SizeDownload
355.5 - Optimizing Gate Sizes ExampleDownload
365.6 - Optimizing the Stages for an inverter pathDownload
375.7 - Optimizing the Stages for a General CircuitDownload
385.8 - Decoder DesignDownload
396.1 - Introduction to Combinational Circuit and assymetric gatesDownload
406.2 - Assymetric Gates analysisDownload
416.3 - Assymetric Gates analysis using short-channel current modelDownload
426.4 - Introduction to Skewed gatesDownload
436.5 - Skewed gates and best P/N ratioDownload
446.6 - vIntroduction to Pseudo NMOSDownload
456.7 - Psudeo NMOS gatesDownload
466.8 - Other Logic FamilyDownload
476.9 - Dynamic Logic and Domino logicDownload
487.1 - Domino gatesDownload
497.2 - Introduction to Stick DiagramDownload
507.3 - Stick Diagram for different gatesDownload
517.4 - Applying Eulers path for stick diagram representationsDownload
527.5 - Multiplexer design and layoutDownload
537.6 - Introduction to InterconnectsDownload
547.7 - Interconnects - RC delay, and EnergyDownload
558.1 - Introduction to crosstalks in interconnectsDownload
568.2 - Transient analysis in CrosstalkDownload
578.3 - Introduction to Repeaters in Interconnect EngineeringDownload
588.4 - Repeater DesignDownload
598.5 - Energy and delay analysis for interconnectwith repeatersDownload
608.6 - Repeater Design and Energy-Delay-Product Download
618.7 - Introduction to PowerDownload
629.1 - Switching Power and Energy EstimationDownload
639.2 - Activity factor and estimating dynamic power for a combinational circuit designDownload
649.3 - Analyzing Dynamic PowerDownload
659.4 - Energy estimation through driving factorDownload
669.5 - Energy expression in terms of delayDownload
679.6 - Voltage ScalingDownload
689.7 - DVFSDownload
6910.1 - Introduction to subthreshold leakage current modelDownload
7010.2 - Subthreshold leakage current and Gate leakage currentDownload
7110.3 - Estimating Static PowerDownload
7210.4 - Introduction to CMOS Latch designDownload
7310.5 - CMOS Latch DesignDownload
7410.6 - CMOS Latch and flipflop designDownload
7511.1 - Static Timing AnalysisDownload
7611.2 - Static Timing Analysis - ContinuedDownload
7711.3 - Static Timing Analysis - Part2Download
7811.4 - Static Timing Analysis - Part2.1Download
7911.5 - Static Timing Analysis - Part3Download
8011.6 - TPDQ and TPCQDownload
8111.7 - Static Timing Analysis - Part4Download
8211.8 - Static Timing Analysis - Part5Download
8311.9 - Static Timing Analysis - Part6Download
8411.10 - SET and CLEAR enabled Latch and Flipflop DesignDownload
8512.1 - 1-bit Adder designDownload
8612.2 - Adder-Part2Download
8712.3 - PG architecture - Part1Download
8812.4 - PG architecture - Part2Download
8912.5 - Carry Skip AdderDownload
9012.6 - Carry Look Ahead and Carry Increment AdderDownload
9112.7 - Other Adder SubsystemsDownload
9212.8 - Approximate Multipliers - Part 1Download
9312.9 - Approximate Multipliers - Part 2Download
9412.10 - Approximate AdderDownload

Sl.No Chapter Name English
11.1 - Understanding SiliconPDF unavailable
21.2 - Introduction to NMOSPDF unavailable
31.3 - NMOS Transistor WorkingPDF unavailable
41.4 - PMOS TransistorPDF unavailable
51.5 - MOS CapacitancesPDF unavailable
61.6 - Non Ideal MOS modelPDF unavailable
71.7 - Short channel current modelPDF unavailable
81.8 - Short channel current model analysisPDF unavailable
92.1 - Channel Length modulation indexPDF unavailable
102.2 - DC characteristics of InverterPDF unavailable
112.3 - Transfer characteristics of InverterPDF unavailable
122.4 - Skewed InverterPDF unavailable
132.5 - Skewed Inverter and threshold voltagePDF unavailable
142.6 - Equivalent of transistors in seriesPDF unavailable
152.7 - Transmission GatePDF unavailable
163.1 - Bad CMOS Buffer - Part1PDF unavailable
173.2 - Bad CMOS Buffer - Part2PDF unavailable
183.3 - Noise margin characteristics of inverterPDF unavailable
193.4 - Noise margin parametersPDF unavailable
203.5 - Introduction to Delay in CMOSPDF unavailable
213.6 - Transient analysis of CMOS InverterPDF unavailable
223.7 - RC approximated delayPDF unavailable
233.8 - Switching ResistancePDF unavailable
244.1 - CMOS Inverter approximated to RC CircuitPDF unavailable
254.2 - Elmore delayPDF unavailable
264.3 - Delay of FO4 inverterPDF unavailable
274.4 - Extracting capacitances of 3-Nand gate for delay estimationPDF unavailable
284.5 - Characterizing Delay of NOR gatePDF unavailable
294.6 - Linear Delay modelPDF unavailable
304.7 - Logical effort and Parasitic delayPDF unavailable
315.1 - Logical effort and Parasitic delay for different gatesPDF unavailable
325.2 - Logical effort for short-channel current modelPDF unavailable
335.3 - Ring Oscillator designPDF unavailable
345.4 - Optimizing Gate SizePDF unavailable
355.5 - Optimizing Gate Sizes ExamplePDF unavailable
365.6 - Optimizing the Stages for an inverter pathPDF unavailable
375.7 - Optimizing the Stages for a General CircuitPDF unavailable
385.8 - Decoder DesignPDF unavailable
396.1 - Introduction to Combinational Circuit and assymetric gatesPDF unavailable
406.2 - Assymetric Gates analysisPDF unavailable
416.3 - Assymetric Gates analysis using short-channel current modelPDF unavailable
426.4 - Introduction to Skewed gatesPDF unavailable
436.5 - Skewed gates and best P/N ratioPDF unavailable
446.6 - vIntroduction to Pseudo NMOSPDF unavailable
456.7 - Psudeo NMOS gatesPDF unavailable
466.8 - Other Logic FamilyPDF unavailable
476.9 - Dynamic Logic and Domino logicPDF unavailable
487.1 - Domino gatesPDF unavailable
497.2 - Introduction to Stick DiagramPDF unavailable
507.3 - Stick Diagram for different gatesPDF unavailable
517.4 - Applying Eulers path for stick diagram representationsPDF unavailable
527.5 - Multiplexer design and layoutPDF unavailable
537.6 - Introduction to InterconnectsPDF unavailable
547.7 - Interconnects - RC delay, and EnergyPDF unavailable
558.1 - Introduction to crosstalks in interconnectsPDF unavailable
568.2 - Transient analysis in CrosstalkPDF unavailable
578.3 - Introduction to Repeaters in Interconnect EngineeringPDF unavailable
588.4 - Repeater DesignPDF unavailable
598.5 - Energy and delay analysis for interconnectwith repeatersPDF unavailable
608.6 - Repeater Design and Energy-Delay-Product PDF unavailable
618.7 - Introduction to PowerPDF unavailable
629.1 - Switching Power and Energy EstimationPDF unavailable
639.2 - Activity factor and estimating dynamic power for a combinational circuit designPDF unavailable
649.3 - Analyzing Dynamic PowerPDF unavailable
659.4 - Energy estimation through driving factorPDF unavailable
669.5 - Energy expression in terms of delayPDF unavailable
679.6 - Voltage ScalingPDF unavailable
689.7 - DVFSPDF unavailable
6910.1 - Introduction to subthreshold leakage current modelPDF unavailable
7010.2 - Subthreshold leakage current and Gate leakage currentPDF unavailable
7110.3 - Estimating Static PowerPDF unavailable
7210.4 - Introduction to CMOS Latch designPDF unavailable
7310.5 - CMOS Latch DesignPDF unavailable
7410.6 - CMOS Latch and flipflop designPDF unavailable
7511.1 - Static Timing AnalysisPDF unavailable
7611.2 - Static Timing Analysis - ContinuedPDF unavailable
7711.3 - Static Timing Analysis - Part2PDF unavailable
7811.4 - Static Timing Analysis - Part2.1PDF unavailable
7911.5 - Static Timing Analysis - Part3PDF unavailable
8011.6 - TPDQ and TPCQPDF unavailable
8111.7 - Static Timing Analysis - Part4PDF unavailable
8211.8 - Static Timing Analysis - Part5PDF unavailable
8311.9 - Static Timing Analysis - Part6PDF unavailable
8411.10 - SET and CLEAR enabled Latch and Flipflop DesignPDF unavailable
8512.1 - 1-bit Adder designPDF unavailable
8612.2 - Adder-Part2PDF unavailable
8712.3 - PG architecture - Part1PDF unavailable
8812.4 - PG architecture - Part2PDF unavailable
8912.5 - Carry Skip AdderPDF unavailable
9012.6 - Carry Look Ahead and Carry Increment AdderPDF unavailable
9112.7 - Other Adder SubsystemsPDF unavailable
9212.8 - Approximate Multipliers - Part 1PDF unavailable
9312.9 - Approximate Multipliers - Part 2PDF unavailable
9412.10 - Approximate AdderPDF unavailable


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