Modules / Lectures
Module NameDownload

Sl.No Chapter Name English
11.1 - Understanding SiliconDownload
Verified
21.2 - Introduction to NMOSDownload
Verified
31.3 - NMOS Transistor WorkingDownload
Verified
41.4 - PMOS TransistorDownload
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51.5 - MOS CapacitancesDownload
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61.6 - Non Ideal MOS modelDownload
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71.7 - Short channel current modelDownload
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81.8 - Short channel current model analysisDownload
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92.1 - Channel Length modulation indexDownload
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102.2 - DC characteristics of InverterDownload
Verified
112.3 - Transfer characteristics of InverterDownload
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122.4 - Skewed InverterDownload
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132.5 - Skewed Inverter and threshold voltageDownload
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142.6 - Equivalent of transistors in seriesDownload
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152.7 - Transmission GateDownload
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163.1 - Bad CMOS Buffer - Part1Download
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173.2 - Bad CMOS Buffer - Part2Download
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183.3 - Noise margin characteristics of inverterDownload
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193.4 - Noise margin parametersDownload
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203.5 - Introduction to Delay in CMOSDownload
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213.6 - Transient analysis of CMOS InverterDownload
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223.7 - RC approximated delayDownload
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233.8 - Switching ResistanceDownload
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244.1 - CMOS Inverter approximated to RC CircuitDownload
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254.2 - Elmore delayDownload
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264.3 - Delay of FO4 inverterDownload
Verified
274.4 - Extracting capacitances of 3-Nand gate for delay estimationDownload
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284.5 - Characterizing Delay of NOR gateDownload
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294.6 - Linear Delay modelDownload
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304.7 - Logical effort and Parasitic delayDownload
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315.1 - Logical effort and Parasitic delay for different gatesDownload
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325.2 - Logical effort for short-channel current modelDownload
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335.3 - Ring Oscillator designDownload
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345.4 - Optimizing Gate SizeDownload
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355.5 - Optimizing Gate Sizes ExampleDownload
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365.6 - Optimizing the Stages for an inverter pathDownload
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375.7 - Optimizing the Stages for a General CircuitDownload
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385.8 - Decoder DesignDownload
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396.1 - Introduction to Combinational Circuit and assymetric gatesDownload
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406.2 - Assymetric Gates analysisDownload
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416.3 - Assymetric Gates analysis using short-channel current modelDownload
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426.4 - Introduction to Skewed gatesDownload
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436.5 - Skewed gates and best P/N ratioDownload
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446.6 - vIntroduction to Pseudo NMOSDownload
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456.7 - Psudeo NMOS gatesDownload
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466.8 - Other Logic FamilyDownload
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476.9 - Dynamic Logic and Domino logicDownload
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487.1 - Domino gatesDownload
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497.2 - Introduction to Stick DiagramDownload
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507.3 - Stick Diagram for different gatesDownload
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517.4 - Applying Eulers path for stick diagram representationsDownload
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527.5 - Multiplexer design and layoutDownload
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537.6 - Introduction to InterconnectsDownload
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547.7 - Interconnects - RC delay, and EnergyDownload
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558.1 - Introduction to crosstalks in interconnectsDownload
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568.2 - Transient analysis in CrosstalkDownload
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578.3 - Introduction to Repeaters in Interconnect EngineeringDownload
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588.4 - Repeater DesignDownload
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598.5 - Energy and delay analysis for interconnectwith repeatersDownload
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608.6 - Repeater Design and Energy-Delay-Product Download
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618.7 - Introduction to PowerDownload
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629.1 - Switching Power and Energy EstimationDownload
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639.2 - Activity factor and estimating dynamic power for a combinational circuit designDownload
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649.3 - Analyzing Dynamic PowerDownload
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659.4 - Energy estimation through driving factorDownload
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669.5 - Energy expression in terms of delayDownload
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679.6 - Voltage ScalingDownload
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689.7 - DVFSDownload
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6910.1 - Introduction to subthreshold leakage current modelDownload
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7010.2 - Subthreshold leakage current and Gate leakage currentDownload
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7110.3 - Estimating Static PowerDownload
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7210.4 - Introduction to CMOS Latch designDownload
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7310.5 - CMOS Latch DesignDownload
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7410.6 - CMOS Latch and flipflop designDownload
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7511.1 - Static Timing AnalysisDownload
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7611.2 - Static Timing Analysis - ContinuedDownload
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7711.3 - Static Timing Analysis - Part2Download
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7811.4 - Static Timing Analysis - Part2.1Download
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7911.5 - Static Timing Analysis - Part3Download
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8011.6 - TPDQ and TPCQDownload
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8111.7 - Static Timing Analysis - Part4Download
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8211.8 - Static Timing Analysis - Part5Download
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8311.9 - Static Timing Analysis - Part6Download
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8411.10 - SET and CLEAR enabled Latch and Flipflop DesignDownload
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8512.1 - 1-bit Adder designDownload
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8612.2 - Adder-Part2Download
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8712.3 - PG architecture - Part1Download
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8812.4 - PG architecture - Part2Download
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8912.5 - Carry Skip AdderDownload
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9012.6 - Carry Look Ahead and Carry Increment AdderDownload
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9112.7 - Other Adder SubsystemsDownload
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9212.8 - Approximate Multipliers - Part 1Download
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9312.9 - Approximate Multipliers - Part 2Download
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9412.10 - Approximate AdderDownload
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