| Module Name | Download |
|---|
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | 1.1 - Understanding Silicon | Download |
| 2 | 1.2 - Introduction to NMOS | Download |
| 3 | 1.3 - NMOS Transistor Working | Download |
| 4 | 1.4 - PMOS Transistor | Download |
| 5 | 1.5 - MOS Capacitances | Download |
| 6 | 1.6 - Non Ideal MOS model | Download |
| 7 | 1.7 - Short channel current model | Download |
| 8 | 1.8 - Short channel current model analysis | Download |
| 9 | 2.1 - Channel Length modulation index | Download |
| 10 | 2.2 - DC characteristics of Inverter | Download |
| 11 | 2.3 - Transfer characteristics of Inverter | Download |
| 12 | 2.4 - Skewed Inverter | Download |
| 13 | 2.5 - Skewed Inverter and threshold voltage | Download |
| 14 | 2.6 - Equivalent of transistors in series | Download |
| 15 | 2.7 - Transmission Gate | Download |
| 16 | 3.1 - Bad CMOS Buffer - Part1 | Download |
| 17 | 3.2 - Bad CMOS Buffer - Part2 | Download |
| 18 | 3.3 - Noise margin characteristics of inverter | Download |
| 19 | 3.4 - Noise margin parameters | Download |
| 20 | 3.5 - Introduction to Delay in CMOS | Download |
| 21 | 3.6 - Transient analysis of CMOS Inverter | Download |
| 22 | 3.7 - RC approximated delay | Download |
| 23 | 3.8 - Switching Resistance | Download |
| 24 | 4.1 - CMOS Inverter approximated to RC Circuit | Download |
| 25 | 4.2 - Elmore delay | Download |
| 26 | 4.3 - Delay of FO4 inverter | Download |
| 27 | 4.4 - Extracting capacitances of 3-Nand gate for delay estimation | Download |
| 28 | 4.5 - Characterizing Delay of NOR gate | Download |
| 29 | 4.6 - Linear Delay model | Download |
| 30 | 4.7 - Logical effort and Parasitic delay | Download |
| 31 | 5.1 - Logical effort and Parasitic delay for different gates | Download |
| 32 | 5.2 - Logical effort for short-channel current model | Download |
| 33 | 5.3 - Ring Oscillator design | Download |
| 34 | 5.4 - Optimizing Gate Size | Download |
| 35 | 5.5 - Optimizing Gate Sizes Example | Download |
| 36 | 5.6 - Optimizing the Stages for an inverter path | Download |
| 37 | 5.7 - Optimizing the Stages for a General Circuit | Download |
| 38 | 5.8 - Decoder Design | Download |
| 39 | 6.1 - Introduction to Combinational Circuit and assymetric gates | Download |
| 40 | 6.2 - Assymetric Gates analysis | Download |
| 41 | 6.3 - Assymetric Gates analysis using short-channel current model | Download |
| 42 | 6.4 - Introduction to Skewed gates | Download |
| 43 | 6.5 - Skewed gates and best P/N ratio | Download |
| 44 | 6.6 - vIntroduction to Pseudo NMOS | Download |
| 45 | 6.7 - Psudeo NMOS gates | Download |
| 46 | 6.8 - Other Logic Family | Download |
| 47 | 6.9 - Dynamic Logic and Domino logic | Download |
| 48 | 7.1 - Domino gates | Download |
| 49 | 7.2 - Introduction to Stick Diagram | Download |
| 50 | 7.3 - Stick Diagram for different gates | Download |
| 51 | 7.4 - Applying Eulers path for stick diagram representations | Download |
| 52 | 7.5 - Multiplexer design and layout | Download |
| 53 | 7.6 - Introduction to Interconnects | Download |
| 54 | 7.7 - Interconnects - RC delay, and Energy | Download |
| 55 | 8.1 - Introduction to crosstalks in interconnects | Download |
| 56 | 8.2 - Transient analysis in Crosstalk | Download |
| 57 | 8.3 - Introduction to Repeaters in Interconnect Engineering | Download |
| 58 | 8.4 - Repeater Design | Download |
| 59 | 8.5 - Energy and delay analysis for interconnectwith repeaters | Download |
| 60 | 8.6 - Repeater Design and Energy-Delay-Product | Download |
| 61 | 8.7 - Introduction to Power | Download |
| 62 | 9.1 - Switching Power and Energy Estimation | Download |
| 63 | 9.2 - Activity factor and estimating dynamic power for a combinational circuit design | Download |
| 64 | 9.3 - Analyzing Dynamic Power | Download |
| 65 | 9.4 - Energy estimation through driving factor | Download |
| 66 | 9.5 - Energy expression in terms of delay | Download |
| 67 | 9.6 - Voltage Scaling | Download |
| 68 | 9.7 - DVFS | Download |
| 69 | 10.1 - Introduction to subthreshold leakage current model | Download |
| 70 | 10.2 - Subthreshold leakage current and Gate leakage current | Download |
| 71 | 10.3 - Estimating Static Power | Download |
| 72 | 10.4 - Introduction to CMOS Latch design | Download |
| 73 | 10.5 - CMOS Latch Design | Download |
| 74 | 10.6 - CMOS Latch and flipflop design | Download |
| 75 | 11.1 - Static Timing Analysis | Download |
| 76 | 11.2 - Static Timing Analysis - Continued | Download |
| 77 | 11.3 - Static Timing Analysis - Part2 | Download |
| 78 | 11.4 - Static Timing Analysis - Part2.1 | Download |
| 79 | 11.5 - Static Timing Analysis - Part3 | Download |
| 80 | 11.6 - TPDQ and TPCQ | Download |
| 81 | 11.7 - Static Timing Analysis - Part4 | Download |
| 82 | 11.8 - Static Timing Analysis - Part5 | Download |
| 83 | 11.9 - Static Timing Analysis - Part6 | Download |
| 84 | 11.10 - SET and CLEAR enabled Latch and Flipflop Design | Download |
| 85 | 12.1 - 1-bit Adder design | Download |
| 86 | 12.2 - Adder-Part2 | Download |
| 87 | 12.3 - PG architecture - Part1 | Download |
| 88 | 12.4 - PG architecture - Part2 | Download |
| 89 | 12.5 - Carry Skip Adder | Download |
| 90 | 12.6 - Carry Look Ahead and Carry Increment Adder | Download |
| 91 | 12.7 - Other Adder Subsystems | Download |
| 92 | 12.8 - Approximate Multipliers - Part 1 | Download |
| 93 | 12.9 - Approximate Multipliers - Part 2 | Download |
| 94 | 12.10 - Approximate Adder | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | 1.1 - Understanding Silicon | Download Verified |
| 2 | 1.2 - Introduction to NMOS | Download Verified |
| 3 | 1.3 - NMOS Transistor Working | Download Verified |
| 4 | 1.4 - PMOS Transistor | Download Verified |
| 5 | 1.5 - MOS Capacitances | Download Verified |
| 6 | 1.6 - Non Ideal MOS model | Download Verified |
| 7 | 1.7 - Short channel current model | Download Verified |
| 8 | 1.8 - Short channel current model analysis | Download Verified |
| 9 | 2.1 - Channel Length modulation index | Download Verified |
| 10 | 2.2 - DC characteristics of Inverter | Download Verified |
| 11 | 2.3 - Transfer characteristics of Inverter | Download Verified |
| 12 | 2.4 - Skewed Inverter | Download Verified |
| 13 | 2.5 - Skewed Inverter and threshold voltage | Download Verified |
| 14 | 2.6 - Equivalent of transistors in series | Download Verified |
| 15 | 2.7 - Transmission Gate | Download Verified |
| 16 | 3.1 - Bad CMOS Buffer - Part1 | Download Verified |
| 17 | 3.2 - Bad CMOS Buffer - Part2 | Download Verified |
| 18 | 3.3 - Noise margin characteristics of inverter | Download Verified |
| 19 | 3.4 - Noise margin parameters | Download Verified |
| 20 | 3.5 - Introduction to Delay in CMOS | Download Verified |
| 21 | 3.6 - Transient analysis of CMOS Inverter | Download Verified |
| 22 | 3.7 - RC approximated delay | Download Verified |
| 23 | 3.8 - Switching Resistance | Download Verified |
| 24 | 4.1 - CMOS Inverter approximated to RC Circuit | Download Verified |
| 25 | 4.2 - Elmore delay | Download Verified |
| 26 | 4.3 - Delay of FO4 inverter | Download Verified |
| 27 | 4.4 - Extracting capacitances of 3-Nand gate for delay estimation | Download Verified |
| 28 | 4.5 - Characterizing Delay of NOR gate | Download Verified |
| 29 | 4.6 - Linear Delay model | Download Verified |
| 30 | 4.7 - Logical effort and Parasitic delay | Download Verified |
| 31 | 5.1 - Logical effort and Parasitic delay for different gates | Download Verified |
| 32 | 5.2 - Logical effort for short-channel current model | Download Verified |
| 33 | 5.3 - Ring Oscillator design | Download Verified |
| 34 | 5.4 - Optimizing Gate Size | Download Verified |
| 35 | 5.5 - Optimizing Gate Sizes Example | Download Verified |
| 36 | 5.6 - Optimizing the Stages for an inverter path | Download Verified |
| 37 | 5.7 - Optimizing the Stages for a General Circuit | Download Verified |
| 38 | 5.8 - Decoder Design | Download Verified |
| 39 | 6.1 - Introduction to Combinational Circuit and assymetric gates | Download Verified |
| 40 | 6.2 - Assymetric Gates analysis | Download Verified |
| 41 | 6.3 - Assymetric Gates analysis using short-channel current model | Download Verified |
| 42 | 6.4 - Introduction to Skewed gates | Download Verified |
| 43 | 6.5 - Skewed gates and best P/N ratio | Download Verified |
| 44 | 6.6 - vIntroduction to Pseudo NMOS | Download Verified |
| 45 | 6.7 - Psudeo NMOS gates | Download Verified |
| 46 | 6.8 - Other Logic Family | Download Verified |
| 47 | 6.9 - Dynamic Logic and Domino logic | Download Verified |
| 48 | 7.1 - Domino gates | Download Verified |
| 49 | 7.2 - Introduction to Stick Diagram | Download Verified |
| 50 | 7.3 - Stick Diagram for different gates | Download Verified |
| 51 | 7.4 - Applying Eulers path for stick diagram representations | Download Verified |
| 52 | 7.5 - Multiplexer design and layout | Download Verified |
| 53 | 7.6 - Introduction to Interconnects | Download Verified |
| 54 | 7.7 - Interconnects - RC delay, and Energy | Download Verified |
| 55 | 8.1 - Introduction to crosstalks in interconnects | Download Verified |
| 56 | 8.2 - Transient analysis in Crosstalk | Download Verified |
| 57 | 8.3 - Introduction to Repeaters in Interconnect Engineering | Download Verified |
| 58 | 8.4 - Repeater Design | Download Verified |
| 59 | 8.5 - Energy and delay analysis for interconnectwith repeaters | Download Verified |
| 60 | 8.6 - Repeater Design and Energy-Delay-Product | Download Verified |
| 61 | 8.7 - Introduction to Power | Download Verified |
| 62 | 9.1 - Switching Power and Energy Estimation | Download Verified |
| 63 | 9.2 - Activity factor and estimating dynamic power for a combinational circuit design | Download Verified |
| 64 | 9.3 - Analyzing Dynamic Power | Download Verified |
| 65 | 9.4 - Energy estimation through driving factor | Download Verified |
| 66 | 9.5 - Energy expression in terms of delay | Download Verified |
| 67 | 9.6 - Voltage Scaling | Download Verified |
| 68 | 9.7 - DVFS | Download Verified |
| 69 | 10.1 - Introduction to subthreshold leakage current model | Download Verified |
| 70 | 10.2 - Subthreshold leakage current and Gate leakage current | Download Verified |
| 71 | 10.3 - Estimating Static Power | Download Verified |
| 72 | 10.4 - Introduction to CMOS Latch design | Download Verified |
| 73 | 10.5 - CMOS Latch Design | Download Verified |
| 74 | 10.6 - CMOS Latch and flipflop design | Download Verified |
| 75 | 11.1 - Static Timing Analysis | Download Verified |
| 76 | 11.2 - Static Timing Analysis - Continued | Download Verified |
| 77 | 11.3 - Static Timing Analysis - Part2 | Download Verified |
| 78 | 11.4 - Static Timing Analysis - Part2.1 | Download Verified |
| 79 | 11.5 - Static Timing Analysis - Part3 | Download Verified |
| 80 | 11.6 - TPDQ and TPCQ | Download Verified |
| 81 | 11.7 - Static Timing Analysis - Part4 | Download Verified |
| 82 | 11.8 - Static Timing Analysis - Part5 | Download Verified |
| 83 | 11.9 - Static Timing Analysis - Part6 | Download Verified |
| 84 | 11.10 - SET and CLEAR enabled Latch and Flipflop Design | Download Verified |
| 85 | 12.1 - 1-bit Adder design | Download Verified |
| 86 | 12.2 - Adder-Part2 | Download Verified |
| 87 | 12.3 - PG architecture - Part1 | Download Verified |
| 88 | 12.4 - PG architecture - Part2 | Download Verified |
| 89 | 12.5 - Carry Skip Adder | Download Verified |
| 90 | 12.6 - Carry Look Ahead and Carry Increment Adder | Download Verified |
| 91 | 12.7 - Other Adder Subsystems | Download Verified |
| 92 | 12.8 - Approximate Multipliers - Part 1 | Download Verified |
| 93 | 12.9 - Approximate Multipliers - Part 2 | Download Verified |
| 94 | 12.10 - Approximate Adder | Download Verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |