Modules / Lectures
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Sl.No Chapter Name English
1Introduction - Digital IC DesignPDF unavailable
2Introduction - Digital IC DesignDownload
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3PN JunctionDownload
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4MOS Capacitor Threshold VoltageDownload
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5MOS Transistor Current ExpressionDownload
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6Body Effect and I-V PlotsDownload
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7Short Channel Transistors - Channel Length ModulationDownload
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8Transistor - 7 - Drain Induced Barrier LoweringDownload
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9Drain Induced Barrier LoweringDownload
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10Sub-Threshold LeakageDownload
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11Substrate and Gate LeakageDownload
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12The PMOS TransistorDownload
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13Transistor CapacitanceDownload
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14Inverter - 1 - CMOS Inverter ConstructionDownload
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15CMOS Inverter ConstructionDownload
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16Voltage Transfer CharacteristicsDownload
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17Load Line AnalysisDownload
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18Trip Point for Short Channel Device InverterDownload
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19Trip Point for Long Channel Device Inverter Download
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20Noise Margin Analysis-1Download
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21Inverter-8 - Noise Margin Analysis-3Download
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22Noise Margin Analysis-3Download
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23Noise Margin Analysis-Long Channel Device Inverter-1Download
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24Noise Margin Analysis-Long Channel Device Inverter-2Download
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25Pass TransistorsDownload
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26NMOS Transistor ON Resistance and Fall DelayDownload
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27Inverter - 14 - Inverter: Transient ResponseDownload
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28Inverter: Transient ResponseDownload
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29Inverter: Dynmaic PowerDownload
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30Inverter: Short Circuit PowerDownload
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31Inverter: Leakage Power and Transistor StacksDownload
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32Stacking Effect and Sleep TransistorsDownload
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33CombCkt - 1 - Implementing Any Boolean Logic FunctionDownload
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34Implementing Any Boolean Logic FunctionDownload
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35Implementing Any Boolean Logic Function: Examples. Gate sizingDownload
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36Gate Sizing Download
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37Logic Gate CapacitanceDownload
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38Gate DelayDownload
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39Parasitic DelayDownload
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40CombCkt - 8 - Logical EffortDownload
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41Logical EffortDownload
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42Gate Delay Download
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43Path Delay Calculation and Optimization FormulationDownload
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44Buffer InsertionDownload
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45Input Ordering and Asymmetric GatesDownload
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46Skewed GatesDownload
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47CombCkt - 13 - Skewed GatesDownload
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48Pseudo NMOS LogicDownload
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49Pseudo NMOS InverterDownload
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50Pseudo NMOS Logical Effort and CVSLDownload
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51Dynamic Circuits and Input MonotonicityDownload
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52Domino Logic and Weak KeepersDownload
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53Transmission Gate LogicDownload
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54CombCkt - 20 - Transmission Gate LogicDownload
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55Ripple Adder IntroductionDownload
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56Full Adder Circuit ImplementationDownload
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57Full Adder OptimizationDownload
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58Carry Skip AdderDownload
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59Carry Select AdderDownload
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60Linear and Square Root Carry Select AdderDownload
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61AM - 6 - Linear and Square Root Carry Select AdderDownload
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62Two's Complement Sign ExtensionDownload
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63Array MultiplierDownload
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64Array Multiplier - Timing AnalysisDownload
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65Carry Save MultiplierDownload
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66Carry Save Multiplier - Signed MultiplicationDownload
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67AM - 12 - Carry Save Multiplier - Signed MultiplicationDownload
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68Time BorrowingDownload
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69Master Slave Flip FlopDownload
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70Flop Timing ParametersDownload
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71Alternate Circuit ImplementationsDownload
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72Clock OverlapDownload
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73SeqCkt - 6 - Clock OverlapDownload
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74Max and Min Delay of Flop Based SystemsDownload
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75Flop Min Delay ConstraintDownload
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76Latch - Max and Min Delay ConstraintsDownload
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77Latch-Timing Analysis with SkewDownload
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78Time Borrowing Download
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79SeqCkt - 12 - Latch-Timing Analysis with SkewPDF unavailable
80SeqCkt - 13 - Time BorrowingDownload
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Sl.No Language Book link
1EnglishNot Available
2BengaliNot Available
3GujaratiNot Available
4HindiNot Available
5KannadaNot Available
6MalayalamNot Available
7MarathiNot Available
8TamilNot Available
9TeluguNot Available