| Name | Download | Download Size |
|---|---|---|
| Lecture Note | Download as zip file | 35M |
| Module Name | Download |
|---|---|
| noc20_ee05_assigment_1 | noc20_ee05_assigment_1 |
| noc20_ee05_assigment_10 | noc20_ee05_assigment_10 |
| noc20_ee05_assigment_11 | noc20_ee05_assigment_11 |
| noc20_ee05_assigment_12 | noc20_ee05_assigment_12 |
| noc20_ee05_assigment_2 | noc20_ee05_assigment_2 |
| noc20_ee05_assigment_3 | noc20_ee05_assigment_3 |
| noc20_ee05_assigment_4 | noc20_ee05_assigment_4 |
| noc20_ee05_assigment_5 | noc20_ee05_assigment_5 |
| noc20_ee05_assigment_6 | noc20_ee05_assigment_6 |
| noc20_ee05_assigment_7 | noc20_ee05_assigment_7 |
| noc20_ee05_assigment_8 | noc20_ee05_assigment_8 |
| noc20_ee05_assigment_9 | noc20_ee05_assigment_9 |
| Sl.No | Chapter Name | MP4 Download |
|---|---|---|
| 1 | Introduction - Digital IC Design | Download |
| 2 | Introduction - Digital IC Design | Download |
| 3 | PN Junction | Download |
| 4 | MOS Capacitor Threshold Voltage | Download |
| 5 | MOS Transistor Current Expression | Download |
| 6 | Body Effect and I-V Plots | Download |
| 7 | Short Channel Transistors - Channel Length Modulation | Download |
| 8 | Transistor - 7 - Drain Induced Barrier Lowering | Download |
| 9 | Drain Induced Barrier Lowering | Download |
| 10 | Sub-Threshold Leakage | Download |
| 11 | Substrate and Gate Leakage | Download |
| 12 | The PMOS Transistor | Download |
| 13 | Transistor Capacitance | Download |
| 14 | Inverter - 1 - CMOS Inverter Construction | Download |
| 15 | CMOS Inverter Construction | Download |
| 16 | Voltage Transfer Characteristics | Download |
| 17 | Load Line Analysis | Download |
| 18 | Trip Point for Short Channel Device Inverter | Download |
| 19 | Trip Point for Long Channel Device Inverter | Download |
| 20 | Noise Margin Analysis-1 | Download |
| 21 | Inverter-8 - Noise Margin Analysis-3 | Download |
| 22 | Noise Margin Analysis-3 | Download |
| 23 | Noise Margin Analysis-Long Channel Device Inverter-1 | Download |
| 24 | Noise Margin Analysis-Long Channel Device Inverter-2 | Download |
| 25 | Pass Transistors | Download |
| 26 | NMOS Transistor ON Resistance and Fall Delay | Download |
| 27 | Inverter - 14 - Inverter: Transient Response | Download |
| 28 | Inverter: Transient Response | Download |
| 29 | Inverter: Dynmaic Power | Download |
| 30 | Inverter: Short Circuit Power | Download |
| 31 | Inverter: Leakage Power and Transistor Stacks | Download |
| 32 | Stacking Effect and Sleep Transistors | Download |
| 33 | CombCkt - 1 - Implementing Any Boolean Logic Function | Download |
| 34 | Implementing Any Boolean Logic Function | Download |
| 35 | Implementing Any Boolean Logic Function: Examples. Gate sizing | Download |
| 36 | Gate Sizing | Download |
| 37 | Logic Gate Capacitance | Download |
| 38 | Gate Delay | Download |
| 39 | Parasitic Delay | Download |
| 40 | CombCkt - 8 - Logical Effort | Download |
| 41 | Logical Effort | Download |
| 42 | Gate Delay | Download |
| 43 | Path Delay Calculation and Optimization Formulation | Download |
| 44 | Buffer Insertion | Download |
| 45 | Input Ordering and Asymmetric Gates | Download |
| 46 | Skewed Gates | Download |
| 47 | CombCkt - 13 - Skewed Gates | Download |
| 48 | Pseudo NMOS Logic | Download |
| 49 | Pseudo NMOS Inverter | Download |
| 50 | Pseudo NMOS Logical Effort and CVSL | Download |
| 51 | Dynamic Circuits and Input Monotonicity | Download |
| 52 | Domino Logic and Weak Keepers | Download |
| 53 | Transmission Gate Logic | Download |
| 54 | CombCkt - 20 - Transmission Gate Logic | Download |
| 55 | Ripple Adder Introduction | Download |
| 56 | Full Adder Circuit Implementation | Download |
| 57 | Full Adder Optimization | Download |
| 58 | Carry Skip Adder | Download |
| 59 | Carry Select Adder | Download |
| 60 | Linear and Square Root Carry Select Adder | Download |
| 61 | AM - 6 - Linear and Square Root Carry Select Adder | Download |
| 62 | Two's Complement Sign Extension | Download |
| 63 | Array Multiplier | Download |
| 64 | Array Multiplier - Timing Analysis | Download |
| 65 | Carry Save Multiplier | Download |
| 66 | Carry Save Multiplier - Signed Multiplication | Download |
| 67 | AM - 12 - Carry Save Multiplier - Signed Multiplication | Download |
| 68 | Time Borrowing | Download |
| 69 | Master Slave Flip Flop | Download |
| 70 | Flop Timing Parameters | Download |
| 71 | Alternate Circuit Implementations | Download |
| 72 | Clock Overlap | Download |
| 73 | SeqCkt - 6 - Clock Overlap | Download |
| 74 | Max and Min Delay of Flop Based Systems | Download |
| 75 | Flop Min Delay Constraint | Download |
| 76 | Latch - Max and Min Delay Constraints | Download |
| 77 | Latch-Timing Analysis with Skew | Download |
| 78 | Time Borrowing | Download |
| 79 | SeqCkt - 12 - Latch-Timing Analysis with Skew | Download |
| 80 | SeqCkt - 13 - Time Borrowing | Download |
| Sl.No | Chapter Name | English |
|---|---|---|
| 1 | Introduction - Digital IC Design | PDF unavailable |
| 2 | Introduction - Digital IC Design | Download To be verified |
| 3 | PN Junction | Download To be verified |
| 4 | MOS Capacitor Threshold Voltage | Download To be verified |
| 5 | MOS Transistor Current Expression | Download To be verified |
| 6 | Body Effect and I-V Plots | Download To be verified |
| 7 | Short Channel Transistors - Channel Length Modulation | Download To be verified |
| 8 | Transistor - 7 - Drain Induced Barrier Lowering | Download To be verified |
| 9 | Drain Induced Barrier Lowering | Download To be verified |
| 10 | Sub-Threshold Leakage | Download To be verified |
| 11 | Substrate and Gate Leakage | Download To be verified |
| 12 | The PMOS Transistor | Download To be verified |
| 13 | Transistor Capacitance | Download To be verified |
| 14 | Inverter - 1 - CMOS Inverter Construction | Download To be verified |
| 15 | CMOS Inverter Construction | Download To be verified |
| 16 | Voltage Transfer Characteristics | Download To be verified |
| 17 | Load Line Analysis | Download To be verified |
| 18 | Trip Point for Short Channel Device Inverter | Download To be verified |
| 19 | Trip Point for Long Channel Device Inverter | Download To be verified |
| 20 | Noise Margin Analysis-1 | Download To be verified |
| 21 | Inverter-8 - Noise Margin Analysis-3 | Download To be verified |
| 22 | Noise Margin Analysis-3 | Download To be verified |
| 23 | Noise Margin Analysis-Long Channel Device Inverter-1 | Download To be verified |
| 24 | Noise Margin Analysis-Long Channel Device Inverter-2 | Download To be verified |
| 25 | Pass Transistors | Download To be verified |
| 26 | NMOS Transistor ON Resistance and Fall Delay | Download To be verified |
| 27 | Inverter - 14 - Inverter: Transient Response | Download To be verified |
| 28 | Inverter: Transient Response | Download To be verified |
| 29 | Inverter: Dynmaic Power | Download To be verified |
| 30 | Inverter: Short Circuit Power | Download To be verified |
| 31 | Inverter: Leakage Power and Transistor Stacks | Download To be verified |
| 32 | Stacking Effect and Sleep Transistors | Download To be verified |
| 33 | CombCkt - 1 - Implementing Any Boolean Logic Function | Download To be verified |
| 34 | Implementing Any Boolean Logic Function | Download To be verified |
| 35 | Implementing Any Boolean Logic Function: Examples. Gate sizing | Download To be verified |
| 36 | Gate Sizing | Download To be verified |
| 37 | Logic Gate Capacitance | Download To be verified |
| 38 | Gate Delay | Download To be verified |
| 39 | Parasitic Delay | Download To be verified |
| 40 | CombCkt - 8 - Logical Effort | Download To be verified |
| 41 | Logical Effort | Download To be verified |
| 42 | Gate Delay | Download To be verified |
| 43 | Path Delay Calculation and Optimization Formulation | Download To be verified |
| 44 | Buffer Insertion | Download To be verified |
| 45 | Input Ordering and Asymmetric Gates | Download To be verified |
| 46 | Skewed Gates | Download To be verified |
| 47 | CombCkt - 13 - Skewed Gates | Download To be verified |
| 48 | Pseudo NMOS Logic | Download To be verified |
| 49 | Pseudo NMOS Inverter | Download To be verified |
| 50 | Pseudo NMOS Logical Effort and CVSL | Download To be verified |
| 51 | Dynamic Circuits and Input Monotonicity | Download To be verified |
| 52 | Domino Logic and Weak Keepers | Download To be verified |
| 53 | Transmission Gate Logic | Download To be verified |
| 54 | CombCkt - 20 - Transmission Gate Logic | Download To be verified |
| 55 | Ripple Adder Introduction | Download To be verified |
| 56 | Full Adder Circuit Implementation | Download To be verified |
| 57 | Full Adder Optimization | Download To be verified |
| 58 | Carry Skip Adder | Download To be verified |
| 59 | Carry Select Adder | Download To be verified |
| 60 | Linear and Square Root Carry Select Adder | Download To be verified |
| 61 | AM - 6 - Linear and Square Root Carry Select Adder | Download To be verified |
| 62 | Two's Complement Sign Extension | Download To be verified |
| 63 | Array Multiplier | Download To be verified |
| 64 | Array Multiplier - Timing Analysis | Download To be verified |
| 65 | Carry Save Multiplier | Download To be verified |
| 66 | Carry Save Multiplier - Signed Multiplication | Download To be verified |
| 67 | AM - 12 - Carry Save Multiplier - Signed Multiplication | Download To be verified |
| 68 | Time Borrowing | Download To be verified |
| 69 | Master Slave Flip Flop | Download To be verified |
| 70 | Flop Timing Parameters | Download To be verified |
| 71 | Alternate Circuit Implementations | Download To be verified |
| 72 | Clock Overlap | Download To be verified |
| 73 | SeqCkt - 6 - Clock Overlap | Download To be verified |
| 74 | Max and Min Delay of Flop Based Systems | Download To be verified |
| 75 | Flop Min Delay Constraint | Download To be verified |
| 76 | Latch - Max and Min Delay Constraints | Download To be verified |
| 77 | Latch-Timing Analysis with Skew | Download To be verified |
| 78 | Time Borrowing | Download To be verified |
| 79 | SeqCkt - 12 - Latch-Timing Analysis with Skew | PDF unavailable |
| 80 | SeqCkt - 13 - Time Borrowing | Download To be verified |
| Sl.No | Language | Book link |
|---|---|---|
| 1 | English | Not Available |
| 2 | Bengali | Not Available |
| 3 | Gujarati | Not Available |
| 4 | Hindi | Not Available |
| 5 | Kannada | Not Available |
| 6 | Malayalam | Not Available |
| 7 | Marathi | Not Available |
| 8 | Tamil | Not Available |
| 9 | Telugu | Not Available |