Now let us consider the sizing of 2 input NAND gate shown in Fig. 4.8. For this gate to have the same pull-down delay (t _PHL) as a minimum sized inverter, the NMOS devices must be made twice as wide so that the equivalent resistance of the pull-down network is the same as the inverter. Since the PMOS devices are in parallel, its size can remain unchanged. In other words, adding devices in series slows down the circuit and devices must be made wider to avoid performance penalty.