4.3.2 Gate delay

The delay of simple gates may be approximated by constructing an “equivalent inverter”. The size of NMOS and PMOS of this inverter reflect the effective strength of the real pull-down and pull-up path in the gate. Thus the propagation delay can be calculated by modeling each transistor of the gate as a resistor in series with the ideal switch. The value of the resistance depends on the power supply voltage and the device width over length ratio. The logic is transformed into an equivalent RC network that includes the effect of internal node capacitances. Fig 4.8 shows the two input NAND gate implementation and the equivalent RC model. It can also be seen that the delay depends on the input patterns. For the case in which both the inputs go from one to zero, results in a smaller delay compared to the case in which only one input goes low. The worst case low to high delay depends for the case in which A = 1 and B changes from 1 to 0. This is because the internal node capacitance also needs to be charged and it slows down the transistor.