When a layout is made in Magic, the system automatically checks design rules. Every time the layout is edited, Magic rechecks for any violation in any of the layout rules. In case of any violation of rules, Magic will display little white dots in the vicinity of the violation. This error paint will stay around until the problem is fixed and when the violation is corrected, the error paint will go away automatically. To verify the layout, Magic creates an .ext netlist containing transistors and capacitors. This can then be incorporated into Spice or sim netlists. All values (cap per area for each layer) are defined in the techfile, so you need to specify for which process you are extracting.

The most important characteristic of the SCMOS technology is that it is flavor-less and scalable: layouts designed using the SCMOS rules may be fabricated in either N-well or P-well technology at a variety of feature sizes. The lambda units used in Magic are dimensionless and can be scaled to dimensions such as 0.6 microns/lambda, 1.0 microns/lambda, 1.5 microns/lambda, etc. In order for SCMOS designs to be fabricated with either N-well or P-well technology, both p-well and n-well contacts must be placed, and where wells and rings are specified explicitly (e.g. in pads) both flavors must be specified. When the circuit is fabricated, one of the flavors of wells, rings, and substrate contacts will be ignored. The SCMOS technology provides two levels of metal. All contacts are to first-level metal.