to all CMOS fabrication processes available through MOSIS. The designer works in the abstract SCMOS layers and metric unit ("lambda"; not to be confused with the channel length modulation parameter l ). Designer then specifies which process and feature size he wants the design to be fabricated. MOSIS maps the SCMOS design onto that process, generating the true logical layers and absolute dimensions required by the process vendor. The designer can often submit exactly the same design, but to a different fabrication process or feature size. MOSIS alone handles the new mapping. All lengths in the layout are in terms of multiples of 's. For example, minimum transistor length is 2, minimum wire spacing is 3, etc. The actual value of can be chosen later depending on the target technology (typically, feature size is 2).

The masks are the interface between a semiconductor manufacturer and the chip designer. In design of a working chip, one should make sure that the mask is prepared according to specific geometric design rules. In addition, interrelationship ship between masks must be ensured to result the correct interconnected set of circuit elements. CAD tools are used to check these two requirements and Magic is a very old layout tool released from Berkeley in 1986. Magic is extraordinarily powerful, and today is still quite capable of large-scale designs, either analog or digital. Magic is available in public domain and recent updates to Magic keep its features on par with "industry standard" layout tools. Other industry standard layout tools come from Mentor Graphics, Cadence, and from in-house CAD groups (e.g. Intel and DEC). Magic is an interactive system for creating and modifying VLSI circuit layouts.