3.8 Technology-related CAD issues

As the layout of an integrated circuit is being prepared, there are layout rules that must be observed in order to ensure that the integrated circuit is manufacturable. Layout rules arise, in part, from the fact that at each mask step in the process, features of the next photo mask must be aligned to features previously defined on the integrated circuit. Even when using precision automatic alignment tools, there is still some error in alignment. In some cases, alignment of two layers is critical to circuit operation. As a result, alignment tolerances impose a limitation of feature size and orientation with respect to other layers on the circuit.

Electrical performance requirements also dictate feature size and orientation with respect to other layers. An example of this is the allowable distance between diffusions supporting a given voltage difference. Understanding the rules associated with electrical performance is most important to the designer if circuits are to be designed that challenge the limits of the technology. The limits for these rules are constrained by the process conditions. Consider the example of wire spacing; a designer wants wires close together that have denser layout. The fabrication process may not be accurate to draw wires too close together. A general set of standard rules for many processes is usually good enough. MOSIS is an economically viable integrated circuit fabrication service where one can purchase prototype and small-volume production quantities of integrated circuits. MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules, which provide a nearly process and metric independent interface