The principal disadvantage of this form of resistor is its non-linearity. That is the resistance is not constant, but depends on the drain-source voltage

Capacitors in CMOS technology

Capacitors in CMOS technology include poly-poly, metal-poly, silicon-silicon and vertical and lateral metal-metal. Many MOS technologies that are used to implement analog functions have two layers of poly silicon. The additional second layer can be used to provide an efficient capacitor structure, an extra layer of inter connect, and also to implement floating gate memory cells that are electrically programmable and optically erasable with UV light. An important aspect of the capacitor structure is the parasitic capacitance associated with each plate. The largest parasitic capacitance exists from the bottom plate to the under lined layer, which could be either the substrate or a well diffusion. This bottom plate parasitic capacitance is typically ten to 30 % of the capacitor itself.

MOS transistor itself can be used as a capacitor when biased in the triode region, the gate forming one plate and the source, drain and the channel forming another. In the processes with only one layer of poly silicon, alternative structures must be used to implement capacitive elements. One approach involves the insertion of an extra mass to reduce the thickness of the oxide on top of the poly silicon layer so that when the interconnect metallization is applied, a capacitor is formed.