To describe the operation of an nMOS enhancement device, note that a positive voltage is applied between the source and the drain (V_DS ). No current flows from the source and the drain at a zero gate bias (that is, V_GS= 0). This is because the source and the drain are insulated from each other by the two reverse-biased diodes as shown in Figure 2.2.However, as a voltage, positive relative to the source and the substrate, is applied to the gate, an electric field is produced across the p-type substrate, This electric field attracts the electrons toward the gate and repels the holes. If the gate voltage is adequately high, the region under the gate changes from p-type to n-type, and it provides a conduction path between the source and the drain. A very thin surface of the p-type substrate is then said to be inverted, and the channel is said to be an n-channel.

To explain in more detail the electrical behaviour of the MOS structure under external bias, assume that the substrate voltage V_SS = 0, and that the gate voltage V_G is the controlling parameter. Three distinct operating regions, namely accumulation, depletion and inversion are identified based on polarity and magnitude of V_G .

If a negative voltage V_G is applied to the gate electrode, the holes in the p-type substrate are attracted towards the oxide-semiconductor interface. As the majority carrier (hole) concentration near the surface is larger than the equilibrium concentration in the substrate, this condition is referred to as the carrier accumulation on the surface. In this case, the oxide electric field is directed towards the gate electrode. Although the hole density increases near the surface in response to the negative gate bias, the minority carrier (electron) concentration goes down as the electrons are repelled deeper into the substrate.