Region 4 : In this region, . As the input voltage V_in is increased beyond V_inv , the n -transistor leaves saturation region and enters linear region, while the p -transistor continues in saturation. The magnitude of both the drain current and the output voltage drops.

Region 5 : In this region, . At this point, the p -transistor is turned off, and the n -transistor is in linear region, drawing a small current, which falls to zero as V_in increases beyond V_DD -| V_tp|, since the p -transistor turns off the current path. The output in this region is .

As may be seen from the transfer curve in Figure 2.12, the transition from "logic 1" state (represented by regions 1 and 2) to “logic 0” state (represented by regions 4 and 5) is quite steep. This characteristic guarantees maximum noise immunity.

ratio : One can explore the variation of the transfer characteristic as a function of the ratio . As noted from (2.15), the logic threshold voltage V_inv depends on the ratio . The CMOS inverter with the ratio =1 allows a capacitive load to charge and discharge in equal times by providing equal current-source and current-sink capabilities. Consider the case of>1. Keeping fixed, if one increases , then the impedance of the pull-down n -transistor decreases. It conducts faster, leading to faster discharge of the capacitive load. This ensures quicker fall of the output voltage V_out , as V_in increases from 0 volt onwards. That is, the transfer characteristic shifts leftwards. Similarly, for a CMOS inverter with <1, the transfer curve shifts rightwards. This is portrayed in Figure 2.13.