One can use a negative latch followed by a positive latch to realize an edge-triggered register, as shown in Figure 1.10. When the clock signal is low, the output of the first stage, normally referred to as the master stage, follows the D input, whereas, the output Q of the second stage, commonly known as the slave stage, retains the previous value. When a transition 0 à 1 takes place in the clock input, the value of the slave output Q freezes at the value of D input existing just before the rising edge of the clock. As the sampling of the input takes place on a clock transition, this register is called a positive edge-triggered register. When the clock remains at logic `1', the master stops sampling the D input and stores the D value at the time of the clock transition. Now, the slave latch allows the complement of the stored master value to pass to the output Q. The D input cannot affect the output Q as the master stage is disconnected from the D input. When the clock makes a transition from `1' to `0', the slave stage is disconnected from the master stage and gets locked to its previous value due to the feedback loop. Also, the master stage begins sampling the D input again.

A negative edge-triggered register is one in which during a 1 → 0 transition, the value of the output Q freezes at the value of D input existing just before the falling edge of the clock. It is realized by reversing the order of the two latches shown in Figure 1.10.