To implement a multiplexer, one can use complementary switches. Figure 1.8 depicts how to realize a 2-input multiplexer in CMOS design style. The circuit shown in Figure 1.8(a) consists of two transmission gates, each consisting of an nMOS and a pMOS transistors. Note that the upper transmission gate allows input A to be passed to the output when the gate control C is at logic '0'. Also, the lower transmission gate transmits the input B to the output when its gate control C is at logic '1'. Thus both the transmission gates are not simultaneously open for their respective input signals to pass to the common output node. This in essence constitutes a 2-input multiplexer with control input C and two data inputs A and B. Figure 1.8(b) shows the commonly used symbol for a 2-input multiplexer.