Fig.2(c) shows a CMOS inverter circuit (NOT gate), where a p-channel and an n-channel MOS transistor is connected in series. A logic '1' input voltage would make T _p (p-channel) turn off and T _n (n-channel) turn on. Hence, the output will be low, pulling Output to logic '0'. A logic '0' Vin voltage, on the other hand, will make T _p turn on and T _n turn off, pulling Output to near V _CC, or logic '1'. The p- and n-channel MOS transistors in the circuit are complementary and they are always in opposite states, i.e., when one of them is 'on' the other is 'off'.