In a digital system the signal is generally sampled at the center of the pulse.

As such if the pulse has constant amplitude, the timing jitter does not affect the sampler out put. However, due to dispersion and due to reshaping, the pulses are rectangular. The sampling jitter then gets converted to the amplitude fluctuation which appears as the noise on the output as shown in Fig.

The sampling jitter is a random variable and hence the fluctuation in current is also a random variable.

Due the fluctuations the mean of the peak current is reduced decreasing the SNR.

The SNR can be restored by increasing the pulse amplitude. Hence there is power penalty for timing jitter.

For raised cosine pulse shaping, the can be analytically calculated.

A plot of power penalty due to timing jitter is shown in the Fig.

The timing jitter penalty obviously depends upon the fractional timing error in comparison to the bit duration. The plot therefore gives the power penalty as function of product of the rms value of the timing jitter and the data rate (inverse of bit duration).

It can be noted that the power penalty very rapidly increases with the timing jitter. When the rms value of the timing jitter is about 0.15, the power penalty becomes infinite. For a Gaussian variable, the peak to peak deviation is about 6 times the standard deviation. A 0.15 fractional jitter means peak to peak variation in sampling time equal to the bit duration. In this case then, the bits can not be sampled properly, and hence the power penalty is infinite, meaning irrespective of the power, the system will never be able to get the data correctly.