VA to PA Translation

• Page faults take a long time: order of ms
  • Need a good page replacement policy
• Once the page fault finishes, the page table entry is updated with the new VPN to PPFN mapping
• Of course, if the valid bit was set, you get the PPFN right away without taking a page fault
• Finally, PPFN is concatenated with the page offset to get the final PA

• Processor now can issue a memory request with this PA to get the necessary data
• Really two memory accesses are needed
• Can we improve on this?

TLB

• Why can't we cache the most recently used translations?
  • Translation Look-aside Buffers (TLB)
  • Small set of registers (normally fully associative)
  • Each entry has two parts: the tag which is simply VPN and the corresponding PTE
  • The tag may also contain a process id
  • On a TLB hit you just get the translation in one cycle (may take slightly longer depending on the design)
  • On a TLB miss you may need to access memory to load the PTE in TLB (more later)
  • Normally there are two TLBs: instruction and data