Implementations

• Do not allow more than one copy of a cache line in M state
  • Need some form of access control mechanism
  • Before a processor does a store it must take “permission” from the current “owner” (if any)
  • Need to know who the current owner is
• Either a processor or main memory
  • Solution1 and Solution2 apply here also
• Latest value must be propagated to the requester
  • Notion of “latest” is very fuzzy
  • Once we know the owner, this is easy
  • Solution1 and Solution2 apply here also
• Invariant: if a cache block is not in M state in any processor, memory must provide the block to the requester
  • Memory must be updated when a block transitions from M state to S state
  • Note that a transition from M to I always updates memory in systems with writeback caches (these are normal writeback operations)
• Most of the implementations of a coherence protocol deals with uncommon cases and races