Cache Coherence: Example

• Consider the same example with a writeback cache
  • P0 has a cached value 5, P1 has 7, P2 has 10, memory has 5 (since caches are not write through)
  • The state of the line in P1 and P2 is M while the line in P0 is clean
  • Eviction of the line from P1 and P2 will issue writebacks while eviction of the line from P0 will not issue a writeback (clean lines do not need writeback )
  • Suppose P2 evicts the line first, and then P1
  • Final memory value is 7: we lost the store x=10 from P2

What Went Wrong?

• For write through cache
  • The memory value may be correct if the writes are correctly ordered
  • But the system allowed a store to proceed when there is already a cached copy
  • Lesson learned: must invalidate all cached copies before allowing a store to proceed
• Writeback cache
  • Problem is even more complicated: stores are no longer visible to memory immediately
  • Writeback order is important Lesson learned: do not allow more than one