Memory Consistency Models

Memory Consistency

• Coherence protocol is not enough to completely specify the output(s) of a parallel program
  • Coherence protocol only provides the foundation to reason about legal outcome of accesses to the same memory location
  • Consistency model tells us the possible outcomes arising from legal ordering of accesses to all memory locations
  • A shared memory machine advertises the supported consistency model; it is a “contract” with the writers of parallel software and the writers of parallelizing compilers
  • Implementing memory consistency model is really a hardware-software tradeoff: a strict sequential model (SC) offers execution that is intuitive, but may suffer in terms of performance; relaxed models (RC) make program reasoning difficult, but may offer better performance

SC

• Recall that an execution is SC if the memory operations form a valid total order i.e. it is an interleaving of the partial program orders
  • Sufficient conditions require that a new memory operation cannot issue until the previous one is completed
  • This is too restrictive and essentially disallows compiler as well as hardware re-ordering of instructions
  • No microprocessor that supports SC implements sufficient conditions
  • Instead, all out-of-order execution is allowed, and a proper recovery mechanism is implemented in case of a memory order violation
  • Let's discuss the MIPS R10000 implementation