In some machines (e.g., SGI Origin 2000) uncached fetch & op is supported
Every such instruction will generate a transaction (may be good or bad depending on the support in memory controller; will discuss later)
Let us assume that the lock location is cacheable and is kept coherent
Every invocation of test & set must generate a bus transaction; Why? What is the transaction? What are the possible states of the cache line holding lock_addr ?
Therefore all lock contenders repeatedly generate bus transactions even if someone is still in the critical section and is holding the lock
