Module 6: Shared Memory Multiprocessors: Consistency and Coherence
  Lecture 12: Cache Coherence Protocols
 


Which One is Better?

  • Difficult to answer
    • Depends on program behavior and hardware cost
  • When is update-based protocol good?
    • What sharing pattern? (large-scale producer/consumer)
    • Otherwise it would just waste bus bandwidth doing useless updates
  • When is invalidation-protocol good?
    • Sequence of multiple writes to a cache line
    • Saves intermediate write transactions
  • Also think about the overhead of initiating small updates for every write in update protocols
    • Invalidation-based protocols are much more popular
    • Some systems support both or maybe some hybrid based on dynamic sharing pattern of a cache line

MSI Protocol

  • Forms the foundation of invalidation-based writeback protocols
    • Assumes only three supported cache line states: I, S, and M
    • There may be multiple processors caching a line in S state
    • There must be exactly one processor caching a line in M state and it is the owner of the line
    • If none of the caches have the line, memory must have the most up-to-date copy of the line
  • Processor requests to cache: PrRd , PrWr
  • Bus transactions: BusRd , BusRdX , BusUpgr , BusWB