Module 6: Shared Memory Multiprocessors: Consistency and Coherence
  Lecture 12: Cache Coherence Protocols
 


Stores

  • Look at stores a little more closely
    • There are three situations at the time a store issues: the line is not in the cache, the line is in the cache in S state, the line is in the cache in one of M, E and O states
    • If the line is in I state, the store generates a read-exclusive request on the bus and gets the line in M state
    • If the line is in S or O state, that means the processor only has read permission for that line; the store generates an upgrade request on the bus and the upgrade acknowledgment gives it the write permission (this is a data-less transaction)
    • If the line is in M or E state, no bus transaction is generated; the cache already has write permission for the line (this is the case of a write hit; previous two are write misses)

Invalidation vs. Update

  • Two main classes of protocols:
    • Invalidation-based and update-based
    • Dictates what action should be taken on a write
    • Invalidation-based protocols invalidate sharers when a write miss (upgrade or readX ) appears on the bus
    • Update-based protocols update the sharer caches with new value on a write: requires write transactions (carrying just the modified bytes) on the bus even on write hits (not very attractive with writeback caches)
    • Advantage of update-based protocols: sharers continue to hit in the cache while in invalidation-based protocols sharers will miss next time they try to access the line
    • Advantage of invalidation-based protocols: only write misses go on bus (suited for writeback caches) and subsequent stores to the same line are cache hits