Cache Coherence

• Intuitive memory model
  • For sequential programs we expect a memory location to return the latest value written to that location
  • For concurrent programs running on multiple threads or processes on a single processor we expect the same model to hold because all threads see the same cache hierarchy (same as shared L1 cache)
  • For multiprocessors there remains a danger of using a stale value: in SMP or DSM the caches are not shared and processors are allowed to replicate data independently in each cache; hardware must ensure that cached values are coherent across the system and they satisfy programmers' intuitive memory model

Example

• Assume a write-through cache i.e. every store updates the value in cache as well as in memory
  • P0: reads x from memory, puts it in its cache, and gets the value 5
  • P1: reads x from memory, puts it in its cache, and gets the value 5
  • P1: writes x=7, updates its cached value and memory value
  • P0: reads x from its cache and gets the value 5
  • P2: reads x from memory, puts it in its cache, and gets the value 7 (now the system is completely incoherent)
  • P2: writes x=10, updates its cached value and memory value