Four Organizations

• In all four organizations caches play an important role in reducing latency and bandwidth requirement
  • If an access is satisfied in cache, the transaction will not appear on the interconnect and hence the bandwidth requirement of the interconnect will be less (shared L1 cache does not have this advantage)
• In distributed shared memory (DSM) cache and local memory should be used cleverly
• Bus-based SMP and DSM are the two designs supported today by industry vendors
  • In bus-based SMP every cache miss is launched on the shared bus so that all processors can see all transactions
  • In DSM this is not the case

Hierarchical Design

• Possible to combine bus-based SMP and DSM to build hierarchical shared memory
  • Sun Wildfire connects four large SMPs (28 processors) over a scalable interconnect to form a 112p multiprocessor
  • IBM POWER4 has two processors on-chip with private L1 caches, but shared L2 and L3 caches (this is called a chip multiprocessor); connect these chips over a network to form scalable multiprocessors
• Next few lectures will focus on bus-based SMPs only