Module 4: "Recap: Virtual Memory and Caches"
  Lecture 8: "Cache Hierarchy and Memory-level Parallelism"
 

Set associative cache

  • The example assumes one cache line per index
    • Called a direct-mapped cache
    • A different access to a line evicts the resident cache line
    • This is either a capacity or a conflict miss
  • Conflict misses can be reduced by providing multiple lines per index
  • Access to an index returns a set of cache lines
    • For an n-way set associative cache there are n lines per set
  • Carry out multiple tag comparisons in parallel to see if any one in the set hits

2-way set associative

Set associative cache

  • When you need to evict a line in a particular set you run a replacement policy
    • LRU is a good choice: keeps the most recently used lines (favors temporal locality)
    • Thus you reduce the number of conflict misses
  • Two extremes of set size: direct-mapped (1-way) and fully associative (all lines are in a single set)
    • Example: 32 KB cache, 2-way set associative, line size of 64 bytes: number of indices or number of sets=32*1024/(2*64)=256 and hence index is 8 bits wide
    • Example: Same size and line size, but fully associative: number of sets is 1, within the set there are 32*1024/64 or 512 lines; you need 512 tag comparisons for each access